Hire the best remote SystemVerilog UVM Developer employees

Discover remote SystemVerilog UVM Developer workers who are looking for their next full-time, part-time or freelance opportunity on Himalayas.

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14 remote workers

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Mahendar Mahi@mahendarmahi

India

Verification Engineer RTL Design Engineer Verilog C++

VLSI verification engineer specializing in UVM and protocol verification.

Experience

Nithu User@nithuuser

India

Verification Engineer UVM Engineer Verilog UVM Methodology

Electronics/ECE graduate specializing in SystemVerilog UVM functional verification.

Experience

Rajesh Valipi@rajeshvalipi

India

Design Verification Engineer Development Engineer Verilog UVM Environments

I’m a Design Verification Engineer specializing in UVM SystemVerilog protocol and VIP development.

Experience

Faisal Saeed Awan@faisalsaeedawan

Pakistan

Asic Verification Engineer Verification Engineer UVM Environments Verilog

I’m a UVM ASIC/SoC Functional Verification Engineer focused on first-pass silicon.

Experience

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Himalayas

Vidhi Radhanpura@vidhiradhanpura

India

Fpga Engineer Verification Engineer UVM Methodology Verilog

Verification engineer specializing in VLSI design and UVM-based functional verification with RTL expertise.

Experience

Andrew Chen@andrewchen4

United States

Asic Verification Engineer Design Verification Engineer Verilog UVM Environments

Senior FPGA/ASIC verification engineer specializing in UVM, constrained-random, coverage-driven closure, and high-speed protocol validation.

Experience

Battinapati Durga Manohar@battinapatidurgamano

India

Fpga Engineer Senior Verification Engineer Data Structures Verilog

VLSI verification engineer skilled in SystemVerilog/UVM, delivering robust RTL and coverage-driven verification.

Bhanu Naga Sarika Neelam@bhanunagasarikaneela

India

RTL Design Engineer VLSI Engineering Verilog RTL Design

RTL verification engineer focused on UVM-based functional coverage for ASIC/SoC.

Experience

Aman K@amank1

India

Verification Engineer Asic Verification Engineer Verilog C++

SoC/IP verification engineer specializing in SV/UVM, protocol VIPs, and debug automation.

Experience

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Himalayas

Keshava jaya ram Chitturi@keshavajayaramchittu

India

Asic Verification Engineer Verification Engineer UVM Environments Verilog

Verification engineer specializing in UVM verification, FPGA validation, and debugging for camera ISP and AI accelerators.

Lavanya-G4 Vlsi User@lavanya-g4vlsiuser

India

RTL Design Engineer Verification Engineer Verilog RTL

Aspiring Design Verification Engineer experienced in Verilog, SystemVerilog and RTL verification.

Experience

ANISH MONDAL@anishmondal

India

Verification Engineer RTL Design Engineer Verilog Data Assertions

VLSI design and verification engineer skilled in RTL and system verification.

Experience

Rubeena Tarannum@rubeenatarannum

Zimbabwe

VLSI Engineering ASIC Design Verification VLSI Design FPGA Verification

VLSI design and verification trainee focused on reliable, standards-compliant IC development.

Experience

Korrapolu Eswar Adithya@korrapolueswaradithy

India

RTL Design Engineer Verification Engineer EDA Playground Verilog

I’m an aspiring VLSI RTL design and verification engineer building ASIC/FPGA-ready modules, testbenches, and SVA-driven validation.

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Himalayas

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Hire the best remote SystemVerilog UVM Developer employees

Finding relevant remote workers

14 remote workers

Finding relevant remote workers

Mahendar Mahi@mahendarmahi

Nithu User@nithuuser

Rajesh Valipi@rajeshvalipi

Faisal Saeed Awan@faisalsaeedawan

Vidhi Radhanpura@vidhiradhanpura

Andrew Chen@andrewchen4

Battinapati Durga Manohar@battinapatidurgamano

Bhanu Naga Sarika Neelam@bhanunagasarikaneela

Aman K@amank1

Keshava jaya ram Chitturi@keshavajayaramchittu

Lavanya-G4 Vlsi User@lavanya-g4vlsiuser

ANISH MONDAL@anishmondal

Rubeena Tarannum@rubeenatarannum

Korrapolu Eswar Adithya@korrapolueswaradithy

Find top remote talent

Find top remote talent

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Find your dream job

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Find your dream job

14 remote workers

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Mahendar Mahi@mahendarmahi

Nithu User@nithuuser

Rajesh Valipi@rajeshvalipi

Faisal Saeed Awan@faisalsaeedawan

Vidhi Radhanpura@vidhiradhanpura

Andrew Chen@andrewchen4

Battinapati Durga Manohar@battinapatidurgamano

Bhanu Naga Sarika Neelam@bhanunagasarikaneela

Aman K@amank1

Keshava jaya ram Chitturi@keshavajayaramchittu

Lavanya-G4 Vlsi User@lavanya-g4vlsiuser

ANISH MONDAL@anishmondal

Rubeena Tarannum@rubeenatarannum

Korrapolu Eswar Adithya@korrapolueswaradithy