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Chirag Dalsaniya

@chiragdalsaniya

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I build and verify RTL designs using Verilog, SystemVerilog, UVM, and coverage-driven verification.

India

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What I'm looking for

I'm looking for a front-end VLSI design and verification role where I can build RTL and UVM verification environments, strengthen my semiconductor expertise, and contribute to impactful design validation work.

I've built SystemVerilog and UVM verification environments for RTL designs at Maven Silicon, using constrained-random stimulus, functional coverage, scoreboards, reference models, assertions, and waveform debugging in Questa Sim.

My projects include verifying an AMBA AHB Bus Matrix, an APB-compliant SPI controller, and dual-port RAM. I also bring PCB layout and manufacturing coordination experience from Circuit System, alongside hands-on work with Vivado, Verilog, SystemVerilog, and digital design components.

Experience

Work history, roles, and key accomplishments

Current

Advanced Design and Verification Trainee

Current

Maven Silicon Softech Pvt. Ltd

Sep 2025 - Present (1 year)

Developed System Verilog-based verification environments for RTL designs, implemented constrained random stimulus generation and functional coverage models, and debugged design issues using Questa Sim.

Verilog Functional Coverage Model Questa Vivado

Production Engineer

Circuit System Pvt. Ltd

Jan 2025 - Jul 2025 (6 months)

Developed and optimized programs for PCB layout design and component placement coordination, collaborating with design and quality teams to ensure manufacturing and testing standards.

PCB Design Component Placement Quality Standards Collaboration

VLSI Design Verification Intern

Indeeksha Digital Pvt. Ltd

May 2024 - Nov 2024 (6 months)

Designed, implemented, and debugged RTL modules using Xilinx Vivado and Questa Sim, working on Verilog, System Verilog, and OOP concepts, and engaged in projects involving AHB, RAM, and FIFO.

Verilog Questa RTL Design Debugging AHB RAMS FIFO