Open to opportunities

Rajesh Valipi

@rajeshvalipi

Message

I’m a Design Verification Engineer specializing in UVM SystemVerilog protocol and VIP development.

India

Message

What I'm looking for

I’m looking for a role where I can build and scale UVM-based verification—especially protocol VIPs (PCIe/AXI/I3C/USB)—with strong ownership of coverage, error injection, and automation to deliver high-quality tape-out readiness.

I’m a Design Verification Engineer with 3.8+ years of experience in SystemVerilog and UVM-based verification, focused on building reliable verification environments and protocol-compliant VIPs.

I specialize in PCIe Transaction Layer VIP development supporting Gen1–Gen6 in both FLIT and Non-FLIT modes, where I drive protocol verification, functional coverage, and error injection using UVM callbacks.

Across my projects, I’ve authored directed and constrained-random testcases, built monitor-based protocol compliance checks, and validated complex behaviors like completion handling, AER error message generation, and link training sequences.

I also bring hands-on experience with AXI4, APB, I3C, UART, and USB protocol validation, using tools like Synopsys VCS and Verdi, plus Python testbench automation and Excel-to-RTL register extraction to streamline verification.

Experience

Work history, roles, and key accomplishments

Design Verification Engineer

Kalatronics Semiconductors Private Limited

Oct 2024 - Mar 2026 (1 year 5 months)

Developed PCIe Transaction Layer VIP supporting Gen1–Gen6 in FLIT and Non-FLIT modes, including TLP generation, monitor-based compliance checks, and completion handling. Implemented UVM callback-based TLP field corruptions for error injection/violation detection and added AER error message generation with directed and constrained-random tests.

PCIe Transaction Layer (TL)TLP Generation UVM Callbacks SVA Synopsys VCS Verdi

Design Verification Engineer

Applied Intelligence Semiconductors Private Limited

Jul 2022 - Oct 2024 (2 years 3 months)

Developed UVM verification environments and VIPs for AXI4, APB, UART, and I3C, including protocol checkers and constrained-random/directed testcases. Verified PCIe Physical Layer across Gen1–Gen5 and validated USB host/device behavior with simulation log-based pass/fail reporting.

UVM Environments AXI4 VIP UART Verification I3C VIP Development PCIe Protocol Verification USB Protocol Validation Synopsys VCS Verdi SVA & Functional Coverage

Education

Degrees, certifications, and relevant coursework

Madanapalle Institute of Technology and Science

Bachelor of Technology, Electronics & Communication Engineering

Grade: 8.64 / 10.0

Earned a B.Tech in Electronics & Communication Engineering from Madanapalle Institute of Technology and Science, graduating in 2022 with a CGPA of 8.64/10.0.