Open to opportunities

Faisal Saeed Awan

@faisalsaeedawan

Message

I’m a UVM ASIC/SoC Functional Verification Engineer focused on first-pass silicon.

Pakistan

Message

What I'm looking for

I’m looking for a Functional Verification Engineer role where I can own UVM-based ASIC/SoC verification, drive coverage closure with rigorous debug, and improve methodology through automation—while applying agentic AI techniques to reduce manual verification effort and enable first-pass silicon.

I’m a results-driven ASIC/SoC Functional Verification Engineer with 3+ years of hands-on experience in UVM-based verification, planning, execution, and coverage-driven debug. I build modular, reusable testbenches and deliver bug-free silicon through disciplined verification lifecycles.

In my current role, I architect SystemVerilog-UVM verification environments for SoC interconnect protocols including AXI, APB, and Die-to-Die Interconnect, while staying technically familiar with UCIe. I develop complex protocol sequences (including CRC validation, FEC, and replay mechanisms), integrate VIP-to-VIP communication models, and close functional coverage prior to design bring-up.

I also streamline verification at the register level using SystemRDL register descriptions and auto-generated UVM RAL models, and I automate regressions with Shell scripting to reduce manual overhead. Alongside day-to-day delivery, I mentor engineers and research Reinforcement Learning-based agentic AI to optimize functional coverage closure and accelerate smarter stimulus generation.

Experience

Work history, roles, and key accomplishments

Current

Design Engineer

Current

Mirasolutions

Mar 2023 - Present (3 years 3 months)

Architected SystemVerilog-UVM verification environments for SoC interconnect protocols (AXI, APB, Die-to-Die), driving D2D link training, CRC validation, and FEC/replay testing to enable first-pass silicon success. Reduced verification development time by 30% by modularizing UVM components for reuse and using coverage-driven verification with automation for regression management.

UVM Environments AXI UCIe Die To Die Interconnect SystemRDL Regression Automation (Shell)

Trainee Design Engineer

Mirasolutions

Oct 2022 - Mar 2023 (5 months)

Built a UVM-based verification environment and reference model for FIFO and ALU to support comprehensive functional verification. Developed modular verification components to improve reuse and maintainability across test scenarios.

UVM Environments FIFO Verification ALU Reference Modeling Regression Testing

Design Verification Trainee

National University of Science and Technology (SINES)

Jun 2022 - Jul 2022 (1 month)

Completed an industry-led UVM verification program, mastering SystemVerilog OOP for testbench architecture and implementing TLM-based communication for modularity. Applied functional coverage techniques to achieve 100% verification closure on digital designs.

Test Architecture