Looking for a job

Tehrim k

@tehrimk

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I build UVM verification environments for AMBA protocols and RTL designs.

India

Message

What I'm looking for

I'm seeking opportunities in ASIC Design Verification, RTL Verification, or SoC Verification where I can build UVM-based verification environments and validate RTL and protocol behavior.

I've built UVM-based verification environments for AXI4, AHB, APB, and synchronous FIFO designs, covering stimulus generation, monitoring, scoreboarding, functional checking, coverage, and waveform debugging.

During my Design Verification internship at Mirafra Technologies, I worked with Verilog, SystemVerilog, and UVM to develop testbenches and verification scenarios for functional behavior, protocol transactions, corner cases, and expected DUT responses.

Experience

Work history, roles, and key accomplishments

Design Verification Intern

Mirafra Technologies

Worked with Verilog, SystemVerilog, and UVM for RTL and functional verification activities. Developed UVM-based verification environments and testbenches, and created verification scenarios covering functional behavior and protocol transactions.

Verilog SystemVerilog UVM Methodology RTL Verification Functional Verification TestBench Development Coverage Analysis