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Wilberth Gutierrez

@wilberthgutierrez

VLSI Design & Verification Engineer at Rydev who developed a pipelined RISC-V SoC and reusable UVM verification environments.

Costa Rica

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At Rydev, I designed and integrated datapath and control logic for a 6-stage pipelined RISC-V SoC, including forwarding and stall logic. I also developed an ALU datapath, SPI-to-bus CDC logic, and a round-robin arbiter.

I developed and maintained a reusable UVM verification environment for the SoC, with regression flows that compared RTL against the RISC-V architectural golden model. I also validated the SoC on a Basys-3 FPGA at 100 MHz using self-checking RISC-V assembly tests.

At Instituto Tecnológico de Costa Rica, I refactored RTL for a multicycle RISC-V processor and verified it through ISS co-simulation. I also built a UVM environment for a UART DUT, reaching 95%+ functional coverage and 100% code coverage.

Experience

Work history, roles, and key accomplishments

IC Design & Verification Engineer Intern

Rydev

Aug 2025 - Jun 2026 (10 months)

Designed and integrated datapath and control logic for a 6-stage pipelined RISC-V SoC, implemented forwarding and stall logic, and developed a reusable UVM verification environment. Drove SpyGlass lint closure and validated the SoC on FPGA.

Research Assistant – Digital Design & Verification

Instituto Tecnológico de Costa Rica

May 2023 - Jun 2026 (3 years 1 month)

Refactored and standardized RTL for a custom multicycle RISC-V processor, resolved lint and CDC issues, ran logic synthesis, and architected UVM environments for UART DUT. Achieved high functional and code coverage.

Education

Degrees, certifications, and relevant coursework

Universidad de Costa Rica

Semiconductor Packaging & Design (ATP & VLSI), Semiconductor Packaging & Design

In progress certification in Semiconductor Packaging & Design (ATP & VLSI).

Cisco Networking Academy

Python Essentials 1, Python

2026 - 2026

Completed Python Essentials 1 in 2026.

Cisco Networking Academy

C++ Essentials 1, C++

2026 - 2026

Completed C++ Essentials 1 in 2026.

Instituto Tecnológico de Costa Rica

Bachelor's Degree, Electronics Engineering

2021 - 2026

Activities and societies: Relevant coursework: Integrated Circuit Design, VLSI Physical Design, Functional Verification of Integrated Circuits, FPGA Workshop, Computer Architecture.

Pursuing a Bachelor's Degree in Electronics Engineering with a thesis on RTL standardization and verification of a multicycle RISC-V processor.