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Ali Sajjad@alisajjad-dev

Pakistan

RTL Design Engineer Verification Engineer Verilog SystemVerilog Assertions

RTL Design and Formal Verification engineer specializing in RISC-V and floating-point units.

Experience

Battinapati Durga Manohar@battinapatidurgamano

India

Fpga Engineer Senior Verification Engineer Data Structures Verilog

VLSI verification engineer skilled in SystemVerilog/UVM, delivering robust RTL and coverage-driven verification.

Lavanya-G4 Vlsi User@lavanya-g4vlsiuser

India

RTL Design Engineer Verification Engineer Verilog RTL

Aspiring Design Verification Engineer experienced in Verilog, SystemVerilog and RTL verification.

Experience

Nithu User@nithuuser

India

Verification Engineer UVM Engineer Verilog UVM Methodology

Electronics/ECE graduate specializing in SystemVerilog UVM functional verification.

Experience

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Himalayas

ANISH MONDAL@anishmondal

India

Verification Engineer RTL Design Engineer Verilog Data Assertions

VLSI design and verification engineer skilled in RTL and system verification.

Experience

Korrapolu Eswar Adithya@korrapolueswaradithy

India

RTL Design Engineer Verification Engineer EDA Playground Verilog

I’m an aspiring VLSI RTL design and verification engineer building ASIC/FPGA-ready modules, testbenches, and SVA-driven validation.

Bhanu Naga Sarika Neelam@bhanunagasarikaneela

India

RTL Design Engineer VLSI Engineering Verilog RTL Design

RTL verification engineer focused on UVM-based functional coverage for ASIC/SoC.

Experience

Faisal Saeed Awan@faisalsaeedawan

Pakistan

Asic Verification Engineer Verification Engineer UVM Environments Verilog

I’m a UVM ASIC/SoC Functional Verification Engineer focused on first-pass silicon.

Experience

Andrew Chen@andrewchen4

United States

Asic Verification Engineer Design Verification Engineer Verilog UVM Environments

Senior FPGA/ASIC verification engineer specializing in UVM, constrained-random, coverage-driven closure, and high-speed protocol validation.

Experience

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Himalayas

Mahendar Mahi@mahendarmahi

India

Verification Engineer RTL Design Engineer Verilog C++

VLSI verification engineer specializing in UVM and protocol verification.

Experience

Vidhi Radhanpura@vidhiradhanpura

India

Fpga Engineer Verification Engineer UVM Methodology Verilog

Verification engineer specializing in VLSI design and UVM-based functional verification with RTL expertise.

Experience

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Hire the best remote SystemVerilog Assertions employees

Finding relevant remote workers

11 remote workers

Finding relevant remote workers

Ali Sajjad@alisajjad-dev

Battinapati Durga Manohar@battinapatidurgamano

Lavanya-G4 Vlsi User@lavanya-g4vlsiuser

Nithu User@nithuuser

ANISH MONDAL@anishmondal

Korrapolu Eswar Adithya@korrapolueswaradithy

Bhanu Naga Sarika Neelam@bhanunagasarikaneela

Faisal Saeed Awan@faisalsaeedawan

Andrew Chen@andrewchen4

Mahendar Mahi@mahendarmahi

Vidhi Radhanpura@vidhiradhanpura

Find top remote talent

Find top remote talent

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Find your dream job

Find your dream job

Find top remote talent

Find your dream job

11 remote workers

Related searches

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Ali Sajjad@alisajjad-dev

Battinapati Durga Manohar@battinapatidurgamano

Lavanya-G4 Vlsi User@lavanya-g4vlsiuser

Nithu User@nithuuser

ANISH MONDAL@anishmondal

Korrapolu Eswar Adithya@korrapolueswaradithy

Bhanu Naga Sarika Neelam@bhanunagasarikaneela

Faisal Saeed Awan@faisalsaeedawan

Andrew Chen@andrewchen4

Mahendar Mahi@mahendarmahi

Vidhi Radhanpura@vidhiradhanpura