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PRANUTHI POLIPOGU

@pranuthipolipogu

ASIC/FPGA Design Engineer who developed an AXI-to-AHB bridge and reusable UVM testbench for protocol verification.

What I'm looking for

I’m seeking to contribute to IP core development and chip design in a fast-paced environment.

I developed a synthesizable AXI-to-AHB bridge and a reusable UVM testbench to verify protocol transactions, handshakes, and data integrity. I used constrained-random and directed tests, assertions, and coverage analysis, with QuestaSim and VCS for debugging.

During my VLSI Design & Verification training at Maven Silicon Softech Private Limited, I worked with AMBA protocols and performed RTL simulation, synthesis, and timing analysis. I also implemented an APB-interfaced UART IP with transmitter, receiver, FIFO buffering, and a register interface.

Experience

Work history, roles, and key accomplishments

ML

VLSI Design & Verification Trainee

Maven Silicon Softech Private Limited

Sep 2025 - Jun 2026 (9 months)

Worked with AMBA protocols (APB, AHB, AXI), SVA, constrained-random verification, and functional coverage. Performed RTL simulation, synthesis, timing analysis, and debugging using QuestaSim, VCS, Vivado, and Design Compiler.

AMBA Protocols APB AHB AXI SystemVerilog Assertions Constraint Random Verification Functional Coverage RTL Simulation Synthesis Static Timing Analysis QuestaSim VCS Vivado Design Compiler

Education

Degrees, certifications, and relevant coursework

ML

Maven Silicon Softech Private Limited

Training Completion Certificate, VLSI Design and Verification

2025 - 2026

Completed VLSI Design and Verification training, covering AMBA protocols, SVA, constrained-random verification, and functional coverage.

VC

Velagapudi Ramakrishna Siddhartha Engineering College

BTech, Electronics and Communication Engineering

2021 - 2025

Grade: 7.80/10

Pursued BTech in Electronics and Communication Engineering with a CGPA of 7.80/10.

Tech stack

Software and tools used professionally

Perl

C

Availability

Looking for a job

Location

India

Authorized to work in

Salary expectations

70k+ INR

Job categories

ASIC FPGA Engineer

Skills

RTL Design ASIC Front End Design Flow FPGA Design Functional Verification UVM Methodology Verilog SystemVerilog AXI AHB APB Synthesis Static Timing Analysis SystemVerilog Assertions Constrained Random Testbenches Directed Testing

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