At Intel, I developed and maintained UVM testbench components for a high-performance Streaming and Interconnect IP block. I verified AXI-to-APB interconnects, including hardware handshakes and Clock Domain Crossing paths.
I automated register verification using UVM RAL and developed custom scoreboards with SystemVerilog Assertions to validate end-to-end data integrity. I also authored coverage code and used Synopsys VCS and Verdi for coverage, waveform analysis, and debugging.
In my Advanced Design Verification Projects, I built a Python-based UVM framework generator for agents, sequences, drivers, and monitors. I also developed AXI4 and APB verification environments to check protocol behavior.
I created a modular UVM testbench library with functional coverage models, SVA, and constraint sets, achieving 100% coverage closure on standalone blocks including FIFOs, FSMs, arbiters, and an ALU.
