At Analog Devices, I own verification planning and execution for packet processing and switching subsystems, from test plan through sign-off. I developed reusable UVM environments and verified packet ordering, QoS enforcement, and back-pressure handling.
On the 800G Ethernet Switch Fabric Verification project, I verified routing across 32 high-speed ports with dynamic load balancing and QoS scheduling. I drove functional coverage above 98% and code coverage above 95% prior to tape-out.
At Texas Instruments (TI), I built reusable UVM testbench architecture for PCIe Gen5 and AXI interconnect verification. I detected and resolved a rare replay buffer overflow issue before silicon and reduced regression debug turnaround by 25% through automation scripting.
Earlier, at ASM Technologies, I designed synthesizable RTL for a low-power data aggregation engine and applied clock-gating techniques that achieved 20% dynamic power savings. At Lattice Semiconductor, I built UVM environments for FPGA IP verification and developed coverage models for SPI and I2C controllers.
