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Akhilesh Ibrahimpet

@akhileshibrahimpet

Message

I build SystemVerilog/UVM verification environments for RTL, memory controllers, and AMBA protocol designs.

India

Message

What I'm looking for

I'm looking for a design verification role where I can build SystemVerilog/UVM environments, verify RTL and AMBA protocols, debug regressions, and grow my expertise in ASIC/SoC verification.

At SION Semiconductors, I developed and functionally verified RTL modules including RTCs, FSM controllers, counters, and memory-related control logic using SystemVerilog environments, simulation, waveform analysis, and RTL debugging.

I've built reusable SystemVerilog/UVM testbenches with constrained-random stimulus, monitors, scoreboards, checkers, TLM communication, assertions, and functional coverage. My project work includes verification environments for AMBA AXI, AHB, and APB protocols, plus SRAM controller verification for read/write operations, address decoding, reset recovery, boundary conditions, and data integrity.

I use QuestaSim regression suites to analyze failures, perform root-cause analysis, and debug RTL and testbench issues.

Experience

Work history, roles, and key accomplishments

Design & Verification Intern

SION Semiconductors

Jul 2025 - Mar 2026 (8 months)

Developed and functionally verified RTL modules including RTC, FSM controllers, counters, and memory-related control logic using SystemVerilog verification environments. Developed reusable SystemVerilog/UVM testbenches and executed simulations and regression suites using QuestaSim.

Functional Verification TestBench Development QuestaSim