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Nithu User

@nithuuser

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Electronics/ECE graduate specializing in SystemVerilog UVM functional verification.

India

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What I'm looking for

I seek a verification role where I can apply SystemVerilog/UVM skills on ASIC/SoC projects, learn from senior engineers, and contribute to robust, coverage-driven verification environments.

I am an Electronics and Communication Engineering graduate focused on functional verification using SystemVerilog and UVM methodologies. I bring hands-on experience in testbench development, constrained-random verification, assertions, and coverage-driven validation.

During internships and academic projects I developed UVM agents (APB, AXI) and testbenches for memory and FIFO designs, implemented drivers, monitors, sequencers, and scoreboards, and worked to close coverage gaps.

I have practical experience with Synopsys VCS Suite, Verdi, EDAPlayground, and scripting in Python, and I am comfortable working in both Linux and Windows environments.

I am passionate about ensuring design quality through rigorous verification strategies, continuous learning in semiconductor verification, and contributing effectively to verification teams.

Experience

Work history, roles, and key accomplishments

ASIC Design & Verification Intern

ChipEdge Technologies Pvt. Ltd.

Jun 2025 - Nov 2025 (5 months)

Contributed to SystemVerilog/UVM testbench component development and created constrained-random testcases for APB-interface designs, improving functional coverage and protocol compliance during training engagements.

TestBench Development Synopsys VCS Verdi