Mahendar Mahi

I am a VLSI Verification Engineer with hands-on experience building UVM environments and achieving full functional coverage for APB, AHB, AXI3, SPI, and I2C protocols. I design and verify RTL components and verification IP using SystemVerilog, constrained-random testing, SVA, and scoreboard methodologies.

In internships and professional training, I developed complete verification environments — drivers, monitors, agents, sequencers, scoreboards, predictors, and virtual interfaces — and ran nightly regressions using Synopsys VCS, QuestaSim, and ModelSim to reach 100% coverage closure. I have implemented directed and constrained-random tests across read/write channels and protocol features, and designed FSM-based I2C and SPI RTL with comprehensive protocol verification.

I take a disciplined, coverage-driven approach to verification, pairing rigorous testbench architecture with practical waveform analysis and regression automation to deliver reliable, production-ready verification results. I am eager to apply these skills on complex SoC or IP verification projects and continue maturing verification infrastructures.