Krishnam Shastri

KS

Looking for a job

Krishnam Shastri

@krishnamshastri

Design Verification Engineer at NXP Semiconductors who achieved formal sign-off for multiple RTL blocks across SoCs.

At NXP Semiconductors, I worked on formal verification for automotive SoCs, developing verification test plans from specifications and block diagrams. I achieved formal sign-off for multiple RTL blocks, including EIM, ERM, and FCCU, and worked on formal connectivity checks and coverage.

On S32N processors, I worked on formal connectivity and coverage checks, and designed Python scripts for testcase re-execution, waveform generation, and GLS report creation. I also generated reusable register-verification C testcases and header files and debugged related failures.

For an in-house I2C verification IP project, I developed a UVM environment and testcases for write and read operations. During training, I built an APB protocol VIP with testcases for reset, read/write validation, and memory control register configuration.

Experience

Work history, roles, and key accomplishments

NS

Current

Formal Verification Engineer

Current

NXP Semiconductors

May 2025 - Present (1 year 5 months)

Worked on S32G vehicle network processors, developing formal verification test plans and achieving formal sign-off for multiple RTL blocks including EIM, ERM, and FCCU. Applied deep bug hunting techniques and managed state-space complexity for proof convergence.

Verdi Synopsys VC Formal VManager SystemVerilog Assertions Formal And Informal Checks Formal Property Verification Coverage Analysis Debugging

NS

Current

Verification Engineer

Current

NXP Semiconductors

Verification Engineer with 3+ years of experience in design verification, currently working as a contractor at NXP Semiconductors. Experienced in formal verification methodologies, SystemVerilog Assertions, and coverage analysis.

SystemVerilog Verilog UVM Methodology Formal Verification SVA Coverage Python Debugging APB AXI Linux Windows Cadence Xcelium VManager Verdi Synopsys VC Formal Git DesignSync

IP

Verification Engineer

In-House Project

Jun 2023 - Jan 2024 (7 months)

Developed Verification Intellectual Property (VIP) for I2C protocol, including UVM environment and testcases for write and read operations.

UVM Methodology I2C Verification Test Bench

Education

Degrees, certifications, and relevant coursework

RV

Rajiv Gandhi Proudyogiki Vishwavidyalaya

Bachelor of Technology, Electronics and Communication Engineering

2019 - 2023

Grade: 8.40 CGPA

Pursued a Bachelor of Technology in Electronics and Communication Engineering, achieving a CGPA of 8.40.

CS

Chameli Devi Public School

Higher Secondary (12th CBSE Board), General

Grade: 78.3%

Completed Higher Secondary education under the CBSE board with 78.3%.

CS

Chameli Devi Public School

Senior Secondary (10th CBSE Board), General

Grade: 89.4%

Completed Senior Secondary education under the CBSE board with 89.4%.

ST

Semiconductor Design Verification Training

Training, Semiconductor Design Verification

Completed a 6-month training program in semiconductor design verification, acquiring skills in Verilog, SV, UVM, and protocols.

Tech stack

Software and tools used professionally

Python

C

Linux

Windows

Git

Availability

Looking for a job

Location

India

Authorized to work in

Salary expectations

1490k+ INR

Job categories

Design Verification Engineer Formal Verification Engineering Verification Engineer

Skills

Formal Verification Formal Property Verification Formal And Informal Checks SystemVerilog Assertions RTL Verification Registration and Verification Coverage Analysis UVM Methodology Digital Logic Design APB AXI AHB I2C Python Verilog

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