VRVidhi Radhanpura
@vidhiradhanpura
Verification engineer specializing in VLSI design and UVM-based functional verification with RTL expertise.
IndiaWhat I'm looking for
I am a Verification Engineer with hands-on experience in VLSI design and verification, UVM testbench development, and RTL implementation using Verilog and SystemVerilog. I have verified multiple IPs and SoC blocks, generated functional and code coverage, and used industry EDA tools like Synopsys VCS, Verdi, Questasim and ISE to achieve verification sign-off.
I bring practical project experience including SPI controller, AHB-to-APB bridge, 1x3 router RTL design and NEORV32 RISC-V SOC block verification, along with teamwork, communication skills, and a commitment to delivering robust, coverage-driven verification environments.
Experience
Work history, roles, and key accomplishments
Education
Degrees, certifications, and relevant coursework
Maven Silicon VLSI Design and Training Center
Professional Training Course, VLSI Design and Verification
2023 - 2024
Activities and societies: Hands-on training with verification methodologies and EDA tools.
Advanced VLSI Design and Verification training focused on practical VLSI design and verification workflows.
V.V.P. Engineering College, Rajkot
Bachelor of Engineering, Electronics and Communication Engineering
2019 - 2023
Activities and societies: VLSI design and verification projects; participation in advanced VLSI training.
Bachelor of Engineering in Electronics and Communication Engineering completed with focus on VLSI concepts and verification methodologies.
Shree P.V. Modi School, Rajkot
Higher Secondary Certificate, Higher Secondary (general)
2018 - 2019
Higher Secondary Certificate completed at Shree P.V. Modi School.
Shree P.V. Modi School, Rajkot
Secondary School Certificate, Secondary Education (general)
2016 - 2017
Secondary School Certificate completed at Shree P.V. Modi School.
Tech stack
Software and tools used professionally
Availability
Location
IndiaAuthorized to work in
Job categories
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