Andrew Chen

I’m a Verification Engineer with 9 years of experience validating FPGA and ASIC designs for high-performance digital systems. My work focuses on IP-level verification, SystemVerilog, and UVM-based verification methodologies that help teams reach production readiness.

I’ve built constrained-random testbenches, functional coverage models, and regression frameworks for complex RTL subsystems running up to 450 MHz across multi-clock architectures exceeding 1 million gates. Using Questa, VCS, and SpyGlass flows (plus Verdi), I’ve delivered coverage-driven verification closure—reaching 98% across regression milestones—and accelerated turnaround by automating regression execution and log analysis with Python and Tcl.

I also partner closely with RTL, firmware, and physical design teams to resolve integration issues, debug RTL-to-gate mismatches, and improve verification closure across 15 ASIC and FPGA tapeout and release cycles. I mentor junior engineers and strengthen scalable verification architecture and debug methodologies, including CDC analysis and linting to reduce synchronization-related failures before hardware bring-up.