Bhanu Naga Sarika Neelam

I’m an M.Tech VLSI Design graduate specializing in RTL design and UVM-based functional verification for ASIC/SoC digital designs in the semiconductor industry. I design synthesizable RTL in SystemVerilog and verify it with a strong coverage mindset, using constrained-random stimulus, functional and code coverage closure, and SVA assertion-based debug.

In my AXI4-Lite Slave Controller project, I delivered timing closure at 150 MHz on Xilinx Artix-7 with zero setup/hold violations after implementation STA. I built a complete UVM verification environment (driver, monitor, scoreboard, coverage collector, sequences) and achieved 95%+ functional coverage and 98% code coverage across 500+ directed and constrained-random test cases, applying SVA to validate AXI handshake protocol compliance.

I also implemented and verified UART, SPI, and I2C protocols by developing reusable UVM testbenches with protocol-specific sequence libraries and SVA-based checking to reach clean final coverage. Beyond RTL verification, I bring automation and signal-focused problem solving—using Tcl/Makefile scripts to reduce regression manual effort by ~60%, and applying Python/GNU Radio work on USRP-based time synchronization to improve timing offset correction accuracy by 35% and reduce latency by 20 ms.