AARTI PRAJAPATI
@aartiprajapati
Design Verification Engineer at Electronics Corporation of India Limited, verifying AXI4-to-AHB-Lite bridges with SystemVerilog and UVM.
IndiaWhat I'm looking for
At Electronics Corporation of India Limited, I verified an AXI4-to-AHB-Lite bridge at block level using SystemVerilog and UVM. My work covered burst conversion, transfer scenarios, and protocol corner cases.
I developed reusable UVM verification components and constrained-random sequences, and implemented assertions and functional coverage for protocol checks.
I also verified AXI, UART, AHB, and APB interfaces, running regressions and debugging failures. I hold an M.Tech in VLSI Design.
Experience
Work history, roles, and key accomplishments
Verification Engineer
Electronics Corporation of India Limited
Mar 2022 - Jul 2026 (4 years 4 months)
Verified AXI-to-AHB bridge, AXI4 interconnect, UART, AHB3-Lite, and APB protocols using UVM and SystemVerilog. Developed UVM environments, assertions, functional coverage, and regression suites.
Education
Degrees, certifications, and relevant coursework
Rajiv Gandhi Proudyogiki Vishwavidyalaya
Master of Engineering, VLSI Design
2023 - 2025
Grade: 8.19/10.0
Pursued a Master of Engineering in VLSI Design, achieving a CGPA of 8.19/10.0.
Rajiv Gandhi Proudyogiki Vishwavidyalaya
Bachelor of Engineering, Engineering
2015 - 2019
Grade: 8.03/10.0
Completed a Bachelor of Engineering, achieving a CGPA of 8.03/10.0.
Availability
Location
IndiaAuthorized to work in
Salary expectations
Job categories
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