At AionSi, I develop UVM test cases for UFS Device operations, including Read/Write commands, Query Responses, and Task Responses. I also implement SystemVerilog Assertions and protocol checkers to verify UFS frame formats and transaction integrity.
I automate regression triage and failure-log analysis with Python, and use Synopsys Verdi to investigate test failures, transaction logs, and waveform issues.
For a memory controller subsystem, I developed UVM sequences for datapath and register access across SDRAM, SSRAM, and Flash Memory. I contributed test cases for multi-memory target scenarios and participated in Gate-Level Simulation, including zero-delay regressions and SDF timing analysis.
I also developed and verified UVM-based VIP for AMBA AXI3 and AXI4, covering protocol scenarios such as unaligned transfers and burst modes. I used Python and Shell scripts to automate testbench configuration, test execution, and coverage collection.
