Open to opportunities

Ali Sajjad

@alisajjad-dev

Message

RTL Design and Formal Verification engineer specializing in RISC-V and floating-point units.

Pakistan

Message

What I'm looking for

I seek RTL and formal verification roles focused on high-performance arithmetic/vector units, collaborative engineering teams, and opportunities to lead complex verification projects and improve silicon quality.

I am an RTL Design and Formal Verification engineer with 3+ years of focused experience on RISC-V scalar and vector architectures, IEEE-754 floating-point units, and DSP datapaths. I specialize in formal property checking and simulation-based verification using Synopsys VC Formal, SystemVerilog, and Python-based CocoTB.

My work includes developing C reference models, performing C2RTL datapath verification, and optimizing RTL for timing and emulation on AWS EC2 Cloud FPGAs. I have formally verified IEEE-754 compliant floating-point units and uncovered 50+ critical arithmetic bugs, and I contributed to open-source RISC-V tooling and FPGA deployment flows under CHIPS Alliance.

I am pursuing roles in RTL Design Engineering and Formal Verification focused on high-performance arithmetic units and vector architectures, and I bring hands-on experience with ASIC flows, emulation, and team leadership delivering AXI4-based subsystems from specification through implementation and verification.

Experience

Work history, roles, and key accomplishments

Current

Formal Verification Engineer

Current

10xEngineers

Mar 2025 - Present (10 months)

Developed SystemVerilog assertions and applied Synopsys VC Formal HECTOR engines to formally verify FIFOs, arbiters, and IEEE-754 floating-point datapaths, uncovering 50+ critical arithmetic bugs and enabling convergence on large proofs.

Formal Verification SystemVerilog Assertions Synopsys VC Formal Datapath Verification (C2RTL)SoftFloat Debugging Python

Design Engineer

Xcelerium

Jun 2022 - Feb 2025 (2 years 8 months)

Designed RISC-V vector and DSP datapaths including a 2048-bit vector multiplier, AXI4 DMA subsystem, and instruction-based clock gating; led RTL implementation, timing optimization, and verification using SystemVerilog and CocoTB.

RTL RISC V

Open Source Contributor

CHIPS Alliance

Modernized FPGA deployment flows and contributed TL-Verilog/RISC-V RTL and microservices to WARP-V and related toolchains, improving deployment on AWS EC2 Cloud FPGAs and community engagement.

Verilog Vivado Vitis AWS EC2 FPGAs RTL Python Documentation