At ChipEdge, I received hands-on training in Verilog and SystemVerilog for RTL design and functional verification. I developed SystemVerilog testbench components and worked on protocol verification and UVM-based testbench development.
For my APB protocol verification project, I developed a UVM-based environment for read/write transactions. I verified the IDLE, SETUP, and ACCESS phases using constrained-random stimulus, assertions, and functional coverage.
For my AXI protocol verification project, I developed a UVM-based environment for read/write transactions and verified VALID/READY handshaking across the address, data, and response channels. I debugged simulation failures using Synopsys VCS and waveform analysis.
I also published a paper on “IOT in Aquaponics enhancing efficiency and Productivity” in INTERNATIONAL JOURNAL OF ADVANE RESEARCH AND INNOVATIVE IDEAS IN EDUCATION.
