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Lavanya-G4 Vlsi User

@lavanya-g4vlsiuser

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Aspiring Design Verification Engineer experienced in Verilog, SystemVerilog and RTL verification.

India

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What I'm looking for

I seek an RTL/verification role in a collaborative engineering team focused on robust verification, learning advanced verification methodologies, and growing in chip design.

I am an aspiring VLSI Design Verification Engineer with hands-on experience in RTL coding, testbench development, and verification using Verilog, SystemVerilog and UVM basics. I focus on functional coverage, assertions (SVA), simulations and methodical debugging to deliver high-quality RTL and verification solutions.

During internships and coursework I developed and verified designs including memory and parameterized FIFO modules, achieving 100% and 95% functional coverage respectively, while debugging with ModelSim and QuestaSim. I have practical exposure to front-end design workflows and OOP-based verification concepts.

I am detail-oriented, committed to continuous learning, and seeking roles as an RTL Design or Verification Engineer where I can apply and expand my verification skills and contribute to robust chip design flows.

Experience

Work history, roles, and key accomplishments

Current

Design Verification Engineer Intern

Current

VLSI Guru

Jul 2025 - Present (4 months)

Completed training in digital design and Verilog with hands-on RTL practice; developing SystemVerilog testbenches, OOP-based verification, coverage, and assertions.

Verilog TestBench Development RTL QuestaSim ModelSim

VLSI Trainee

SURE Trust

Oct 2024 - Apr 2025 (6 months)

Completed a comprehensive VLSI course covering digital design, Verilog/RTL, SystemVerilog, DFT, and physical design with hands-on front-end and verification projects.

RTL Verilog TestBench Development DFT Basics Vivado EDA Playground