Open to opportunities

Aditya Raut

@adityaraut3

Message

I design and verify FPGA-based digital interfaces and high-speed arithmetic RTL.

India

Message

What I'm looking for

I'm looking for opportunities in RTL design and VLSI design verification where I can build and verify digital interfaces, develop SystemVerilog testbenches, and deepen my FPGA, verification, and timing-analysis skills.

I'm building FPGA-based digital designs and verification environments, including Radix-4 Booth multipliers, SPI interfaces, and UART TX/RX modules.

At Provlogic Technologies, I work on RTL design and functional verification using Verilog and SystemVerilog, developing testbenches, debugging simulations, and analyzing waveforms in ModelSim and QuestaSim. I apply UART, FSM, digital logic, verification methodology, and static timing analysis concepts in industry-oriented projects.

My project work includes parameterized SPI and UART designs with modular, self-checking SystemVerilog environments for directed, random, and constrained-random testing. I also evaluate FPGA multiplier architectures for timing, area utilization, estimated power, and hardware efficiency.

Experience

Work history, roles, and key accomplishments

Current

Design Verification Intern

Current

Provlogic Technologies

Jun 2026 - Present (2 months)

Working on RTL design and functional verification using Verilog/SystemVerilog, including simulation, testbench development, debugging, and waveform analysis with ModelSim and QuestaSim. Applying UART protocol, FSM Design, Digital Logic Design, Verification Methodology, and Static Timing Analysis (STA) concepts in industry-oriented verification projects.

Verilog ModelSim QuestaSim UART Digital Logic Design