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NagendraReddy User

@nagendrareddyuser1

Design Verification Engineer focused on SystemVerilog and UVM, with an AXI4 verification environment covering all five channels.

India

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What I'm looking for

I'm looking for a Design Verification Engineer role. I'm available for immediate joining and open to relocation.

I built a UVM-based environment to verify AXI4 protocol functionality, including read and write transactions across all five channels. I used directed and constrained-random scenarios to check FIXED, INCR, and WRAP burst transfers.

For the AXI4 project, I implemented a scoreboard to compare expected and actual transaction results. I also used SystemVerilog Assertions and functional coverage to check protocol compliance and verification completeness.

I debugged simulation failures through waveform analysis in the QuestaSim Wave window. My verification work also covered VALID/READY handshaking, backpressure, and protocol behavior.

In smaller projects, I designed a synchronous FIFO, a D flip-flop, and an FSM-based traffic light controller in Verilog, then verified their behavior using SystemVerilog and UVM. I completed Front-End VLSI Design and Verification training at VLSI Guru, Bangalore.

Experience

Work history, roles, and key accomplishments

Design Verification Engineer

VLSI Guru

Completed professional training in Verilog, SystemVerilog, UVM, SVA, and AXI protocols. Gained hands-on experience in RTL design and UVM verification projects using QuestaSim, ModelSim, and EDA Playground.