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Srikanta S M

@srikantasm

Staff Verification Engineer at Krutrim verifying IEEE 754 floating-point IP for an AI accelerator chiplet using SystemVerilog and UVM.

India

Message

What I'm looking for

I’m seeking an opportunity to learn and understand computing algorithms in Server, HPC, and AI applications, and to contribute my skills to enhancing compute performance in the ASIC chiplet ecosystem.

At Krutrim, I verify an AI accelerator chiplet’s IEEE floating-point core computing using SystemVerilog and UVM. My work includes multi-format floating-point addition, multiplication, and parallel adder IP, as well as a matrix multiplication subsystem.

At AMD, I worked on server SoC chiplet verification across the IO Die, Classic Core Die, and Dense Core Die. I planned and executed SMU subsystem verification and boot-code tests for IOD and CCD core processors, and analyzed fuse flows and handshaking between chiplets.

At SeviTech Systems Pvt, I contributed to subsystem verification for a DDIC project for Silicon Works, including power management between the PMIC and DDIC and clock management between the DSI Host and DDIC. I also worked on UVM testbench architecture and subsystem reusability and reliability analysis.

At Blueberry Semiconductors Private Limited, I verified VESA DSC encoder and decoder IP and a GNSS SoC, including AHB interconnects, SGDMA access control, AHB-APB bridges, and CAN 2.0 FD IP. Earlier, at Cybrain Software Solutions, I developed UVCs for standard protocols and testbench components for SoC subsystem verification.

Experience

Work history, roles, and key accomplishments

Current

Staff Verification Engineer

Current

Krutrim

Jul 2024 - Present (2 years 3 months)

AI Accelerator Chiplet Verification (IEEE Floating Point Core Computing) using SV and UVM. Individual contribution roles along with project management.

UVM Methodology IEEE 754 Float Project Management Coverage Analysis

Senior Silicon Design Engineer

AMD

Dec 2021 - Jun 2024 (2 years 6 months)

Server SOC Chiplet Verification (IO Die/Classic Core Die/Dense Core Die) using SV and UVM. Individual contribution roles along with project management.

UVM Methodology SoC Verification SMU Bootloaders Fuse Flow Chiplet Technology

Project Lead Design Verification Engineer

SeviTech Systems Pvt

Dec 2019 - Oct 2021 (1 year 10 months)

DDIC (Display Driver IC) - Sub System level Verification - (Silicon Works, South Korea). Involved in SOC test bench architecture planning for optimized version of UVM.

UVM Methodology SoC Verification Power Management Clock Management DSI DDIC

Verification Engineer

Blueberry Semiconductors Private Limited

Nov 2017 - Dec 2019 (2 years 1 month)

VESA DSC (Video Codec Compression) - IP Verification (Synopsys, India) and HAMSA (GNSS chiplet) - SOC Verification (Ensilica, India).

UVM Methodology VESA DSC GNSS AHB APB CAN SGDMA

Junior Engineer

Cybrain Software Solutions

Jul 2015 - Jul 2017 (2 years)

Learnt architecture of testbench for verifying IP's using SV and UVM tools. UVC development for standard protocols like I2C/SPI/CAN/UART/APB.

UVM Methodology I2C SPI CAN UART APB Assertions

ASIC DV Trainee

Maven Silicon

Sep 2014 - Feb 2015 (5 months)

Enrolled in 'Advanced VLSI Design and Verification' course at Maven Silicon. Worked on design and verification of Router 1x3 following the Ethernet protocol as a mini project.

SystemVerilog UVM Methodology Code Coverage FPGA Perl SVA STA

Intern

Embedded Software Development Systems Inc.

Dec 2013 - Jan 2014 (1 month)

Software development services for defense related projects. Architectural study and documentation of micro processors like ARM, Cortex 7 and some Infineon processors.

Arm Cortex Infineon Linkers Compiler Debuggers