At Aura Semiconductor, I verify a mixed-signal Smart Power Stage (SPS) IC, covering digital control logic and analog blocks with a UVM-based testbench. I implemented a UVM RAL model for the PIF register space and verified power-up sequencing, test modes, I2C access, and EFUSE operations.
I developed directed and constrained-random tests, SVA assertions, and functional coverage, and drove coverage closure toward 100% with documented, reviewed waivers. I also built Verilog-AMS behavioral models and ran closed-loop mixed-signal simulations that uncovered corner-case bugs.
I maintain and extend regression automation scripts in Python, Perl, TCL, and Makefile, and have supported four major tape-outs plus incremental tape-outs. In personal projects, I built UVM verification for an APB-based UART Master Core and designed and verified a 1x3 router.
