Hire the best remote Verification & Validation Engineer employees

Discover remote Verification & Validation Engineer workers who are looking for their next full-time, part-time or freelance opportunity on Himalayas.

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29 remote workers

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Vidhi Radhanpura@vidhiradhanpura

India

Fpga Engineer Verification Engineer UVM Methodology Verilog

Verification engineer specializing in VLSI design and UVM-based functional verification with RTL expertise.

Experience

Nithu User@nithuuser

India

Verification Engineer UVM Engineer Verilog UVM Methodology

Electronics/ECE graduate specializing in SystemVerilog UVM functional verification.

Experience

Keshava jaya ram Chitturi@keshavajayaramchittu

India

Asic Verification Engineer Verification Engineer UVM Environments Verilog

Verification engineer specializing in UVM verification, FPGA validation, and debugging for camera ISP and AI accelerators.

Rajesh Valipi@rajeshvalipi

India

Design Verification Engineer Development Engineer Verilog UVM Environments

I’m a Design Verification Engineer specializing in UVM SystemVerilog protocol and VIP development.

Experience

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Himalayas

Nitu Kumari@nitukumari

India

Test Engineer Hardware Engineer ASIC PCIe

Experienced ASIC Verification Engineer specializing in pre-silicon validation.

Experience

Faisal Saeed Awan@faisalsaeedawan

Pakistan

Asic Verification Engineer Verification Engineer UVM Environments Verilog

I’m a UVM ASIC/SoC Functional Verification Engineer focused on first-pass silicon.

Experience

Aafreen Qureshi@aafreenqureshi

India

Verification And Validation Engineer Validation Engineer Post Silicon Validation Functional Testing

System Software Validation Engineer specialized in post-silicon security validation and debugging.

Anup Rahangdale@anuprahangdale

United States

Validation Engineer Test Lead And Verification Root Cause Analysis

Experienced automotive systems verification engineer specializing in ECU calibration and validation.

Experience

Aishwarya Subramanian@aishwaryasubramanian

India

Design Engineer Test Engineer Verilog UVM Methodology

Skilled design verification engineer focused on optimizing testbench performance.

Experience

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Himalayas

Mahendar Mahi@mahendarmahi

India

Verification Engineer RTL Design Engineer Verilog C++

VLSI verification engineer specializing in UVM and protocol verification.

Experience

Aman K@amank1

India

Verification Engineer Asic Verification Engineer Verilog C++

SoC/IP verification engineer specializing in SV/UVM, protocol VIPs, and debug automation.

Experience

Battinapati Durga Manohar@battinapatidurgamano

India

Fpga Engineer Senior Verification Engineer Data Structures Verilog

VLSI verification engineer skilled in SystemVerilog/UVM, delivering robust RTL and coverage-driven verification.

aakriti jha@aakritijha

India

Validation Engineer Embedded Systems Engineer Embedded Systems Real Time Systems

Computer engineer specializing in validation and embedded systems with regulatory expertise.

Experience

Lavanya-G4 Vlsi User@lavanya-g4vlsiuser

India

RTL Design Engineer Verification Engineer Verilog RTL

Aspiring Design Verification Engineer experienced in Verilog, SystemVerilog and RTL verification.

Experience

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Himalayas

Reshma resh@reshmaresh

India

Embedded Systems Engineer Validation Engineer Remote DSpace

HIL Validation Engineer specializing in ECU validation, CAN communications, and test automation.

Experience

Haley Smith@haleysmith1

United States

Verification And Validation Engineer Risk Management Engineering 21 CFR 820 EN 60601

Design assurance engineer specializing in regulated medical and aerospace systems.

Andrew Chen@andrewchen4

United States

Asic Verification Engineer Design Verification Engineer Verilog UVM Environments

Senior FPGA/ASIC verification engineer specializing in UVM, constrained-random, coverage-driven closure, and high-speed protocol validation.

Experience

Bhanu Naga Sarika Neelam@bhanunagasarikaneela

India

RTL Design Engineer VLSI Engineering Verilog RTL Design

RTL verification engineer focused on UVM-based functional coverage for ASIC/SoC.

Experience

Tanmay Rambha@tanmayrambha

India

IP Verification SoC Verification Verilog Python

I bring hands-on UVM, SVA, and formal verification for SPI and AXI4-Lite IP/SoC validation.

Experience

Rubeena Tarannum@rubeenatarannum

Zimbabwe

VLSI Engineering ASIC Design Verification VLSI Design FPGA Verification

VLSI design and verification trainee focused on reliable, standards-compliant IC development.

Experience

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Hire the best remote Verification & Validation Engineer employees

Finding relevant remote workers

29 remote workers

Finding relevant remote workers

Vidhi Radhanpura@vidhiradhanpura

Nithu User@nithuuser

Keshava jaya ram Chitturi@keshavajayaramchittu

Rajesh Valipi@rajeshvalipi

Nitu Kumari@nitukumari

Faisal Saeed Awan@faisalsaeedawan

Aafreen Qureshi@aafreenqureshi

Anup Rahangdale@anuprahangdale

Aishwarya Subramanian@aishwaryasubramanian

Mahendar Mahi@mahendarmahi

Aman K@amank1

Battinapati Durga Manohar@battinapatidurgamano

aakriti jha@aakritijha

Lavanya-G4 Vlsi User@lavanya-g4vlsiuser

Reshma resh@reshmaresh

Haley Smith@haleysmith1

Andrew Chen@andrewchen4

Bhanu Naga Sarika Neelam@bhanunagasarikaneela

Tanmay Rambha@tanmayrambha

Rubeena Tarannum@rubeenatarannum

Find top remote talent

Find top remote talent

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Get matched with your dream remote job

Get matched with your dream remote job

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Get matched with your dream remote job

29 remote workers

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Vidhi Radhanpura@vidhiradhanpura

Nithu User@nithuuser

Keshava jaya ram Chitturi@keshavajayaramchittu

Rajesh Valipi@rajeshvalipi

Nitu Kumari@nitukumari

Faisal Saeed Awan@faisalsaeedawan

Aafreen Qureshi@aafreenqureshi

Anup Rahangdale@anuprahangdale

Aishwarya Subramanian@aishwaryasubramanian

Mahendar Mahi@mahendarmahi

Aman K@amank1

Battinapati Durga Manohar@battinapatidurgamano

aakriti jha@aakritijha

Lavanya-G4 Vlsi User@lavanya-g4vlsiuser

Reshma resh@reshmaresh

Haley Smith@haleysmith1

Andrew Chen@andrewchen4

Bhanu Naga Sarika Neelam@bhanunagasarikaneela

Tanmay Rambha@tanmayrambha

Rubeena Tarannum@rubeenatarannum