Keshava jaya ram Chitturi

I am a proactive Verification Engineer with nearly three years of focused experience in UVM verification of Camera ISP IPs and AI accelerators. I specialize in SystemVerilog RTL verification, coverage-driven methodologies, and thorough debugging of complex designs.

At Samsung R&D I contributed to black-box verification of flagship Camera ISP IPs and built an FPGA validation environment from scratch on the ZCU102 platform to enable seamless hardware-software prototyping. My work helped find critical bugs and prepared the prototype flow for next-generation IPs.

Previously at BrainChip Systems I participated in UVM verification of NPU modules inside a Network-on-Chip fabric supporting Vision Transformers, CNNs and LLM-related accelerators, driving agent ownership and discovering critical functional issues in floating-point operations.

I deliver reproducible verification flows and automation: I developed UVM testbenches achieving high functional and code coverage, automated coverage analysis with Python to accelerate closure, and implemented FPGA-based validation frameworks that improved readiness and reduced time-to-prototype.