Tanmay Rambha

I’m a hardware verification-focused engineer with hands-on experience in UVM, SVA, and formal verification (SymbiYosys/Bitwuzla) applied to SPI and AXI4-Lite designs. I build complete verification environments—constrained-random testbenches, functional coverage, and property-based formal proofs—so teams can trust the behavior across legal scenarios.

During my VLSI Design & Validation internship at HCL Technologies, I built a complete UVM verification environment for a parameterized SPI master-slave design. It included separate master/slave agents, a dual-channel scoreboard, fault injection infrastructure, six functional covergroups, and 14 concurrent SVA assertions—achieving 99.8% average functional coverage across 610 transactions with zero failures.

I also applied formal verification to the SPI system using SymbiYosys (Bitwuzla backend), where I wrote 6 assertions and 6 assumptions and resolved 4 counterexamples through root-cause analysis. I achieved BMC PASS at depth 80 and cover PASS across multiple configurations, and I formally verified the SPI slave under 4 independent clock triggers with clk2fflogic, resolving counterexamples and documenting a clocking limitation with an architectural fix.

Alongside verification work, I’ve done hardware research and IP-style design through my Research Intern role at IIT Hyderabad. I configured STM32 hardware timers for synchronized multi-phase clock generation and implemented a 12-bit ADC + DMA pipeline for CCD readout, plus a Python-based USB-CDC interface for real-time streaming and visualization.