Rubeena Tarannum

I’m a VLSI design and verification trainee who wants to contribute to the design and development of integrated circuits in the semiconductor industry. I’m trained through “Advanced VLSI Design and Verification” at VLSI FIRST, and I’m focused on delivering designs that are correct, robust, and standards-aligned.

In my projects, I implemented a 10-Gigabit Ethernet 10GE MAC (frame assembly/disassembly, CRC-based error detection, flow control, and IEEE 802.3 compliance) and worked on an Efficient Operand Divided Hybrid Adder for error-tolerant applications. I also built FPGA-based image processing using ZYNQ FPGA with Verilog HDL in Xilinx Vivado, covering filtering operations like blurring/sharpening, edge detection, and convolution.

I’m especially motivated by verification work: I developed and executed a USB 2.0 functional verification environment using UVM to validate enumeration, data transfers, and error handling against the USB 2.0 specification. I enjoy turning requirements into reliable verification and using tools like QuestaSim, Static Timing Analysis (STA), and protocol-focused verification to improve project success.