Hire the best remote Xilinx Vivado employees

Discover remote Xilinx Vivado workers who are looking for their next full-time, part-time or freelance opportunity on Himalayas.

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28 remote workers

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vahram sim@vahramsim

Armenia

FPGA Design Engineer Verification Engineer Verilog RTL

Junior FPGA design engineer specializing in RTL, verification, and board bring-up.

Experience

Junior FPGA Design Engineer

Siemens AG

Aug 2022 - Aug 2024 (2 years)

FPGA Design Intern

Infineon Technologies

May 2021 - Aug 2022 (1 year 3 months)

Student Research Assistant

AMD (Xilinx)

Sep 2020 - May 2021 (8 months)

FPGA Design Engineer Verification Engineer Embedded Systems Engineer Digital Design Engineer

Rubeena Tarannum@rubeenatarannum

Zimbabwe

VLSI Engineering ASIC Design Verification VLSI Design FPGA Verification

VLSI design and verification trainee focused on reliable, standards-compliant IC development.

Experience

Noor E Saniya@nooresaniya

India

Embedded Systems Engineer Hardware Design Engineer Verilog Python

FPGA and hardware developer focused on verification-ready radar electronics.

Experience

Prateeksha Hiremath@prateekshahiremath

India

Fpga Engineer VLSI Design Intern Verilog Python

M.Tech candidate in VLSI & Nanotech specializing in FPGA and embedded systems.

Experience

dasari lakshmiprasanna@dasarilakshmiprasann

India

Embedded AI Engineer FPGA Design Engineer Remote Verilog

I build low-latency edge AI on FPGA using hardware-accelerated ML systems.

Experience

Saad Qureshi@saadqureshi1

United States

Digital Designer FPGA Design Engineer Digital Engineering Processes Project Management

Dedicated Electrical Engineer with over ten years of experience.

Experience

Korrapolu Eswar Adithya@korrapolueswaradithy

India

RTL Design Engineer Verification Engineer EDA Playground Verilog

I’m an aspiring VLSI RTL design and verification engineer building ASIC/FPGA-ready modules, testbenches, and SVA-driven validation.

Keerthi Sree@keerthisree

India

Physical Design Engineer VLSI Design Intern Synopsys ICC2 Dc_shell

VLSI Physical Design Engineer skilled in 28nm PNR flows.

Experience

praveen kumar bolla@praveenkumarbolla

India

Fpga Engineer RTL Design Engineer VLSI Matlab

ECE graduate focused on embedded systems and VLSI design, delivering practical hardware and RTL solutions.

Experience

Bhanu Naga Sarika Neelam@bhanunagasarikaneela

India

RTL Design Engineer VLSI Engineering Verilog RTL Design

RTL verification engineer focused on UVM-based functional coverage for ASIC/SoC.

Experience

Keshava jaya ram Chitturi@keshavajayaramchittu

India

Asic Verification Engineer Verification Engineer UVM Environments Verilog

Verification engineer specializing in UVM verification, FPGA validation, and debugging for camera ISP and AI accelerators.

Aavash Basnet@aavashbasnet

India

Embedded Systems Engineer VLSI Design Intern C#Java

Aspiring EEE engineer focused on embedded systems, VLSI, and sustainable energy solutions.

Experience

Ahmad Abdullah@ahmadabdullah2

Pakistan

RTL Design Engineer Senior Chip Architecture Engineer C#Verilog

Digital IC design intern focused on RTL, RISC-V processors, and hardware verification.

Experience

Mahendar Mahi@mahendarmahi

India

Verification Engineer RTL Design Engineer Verilog C++

VLSI verification engineer specializing in UVM and protocol verification.

Experience

Omkar Gaonkar@omkargaonkar

India

Software Engineer Electrical Engineer Verilog C++

Passionate Electronics and Communication Engineer

Experience

ANISH MONDAL@anishmondal

India

Verification Engineer RTL Design Engineer Verilog Data Assertions

VLSI design and verification engineer skilled in RTL and system verification.

Experience

SANDHYA CHILUKURI@sandhyachilukuri

India

Academic Coordinator Online Tutor Communications Engineering online tutoring

Electronics and Communication engineer and experienced online tutor delivering engaging learning.

Ali Sajjad@alisajjad-dev

Pakistan

RTL Design Engineer Verification Engineer Verilog SystemVerilog Assertions

RTL Design and Formal Verification engineer specializing in RISC-V and floating-point units.

Experience

Prajyot Patil@prajyotpatil

India

VLSI Design Intern Senior Verification Engineer VLSI Design CMOS Layout Design

Electronics engineer specializing in VLSI design, verification, and CADENCE workflows.

Experience

Andrew Chen@andrewchen4

United States

Asic Verification Engineer Design Verification Engineer Verilog UVM Environments

Senior FPGA/ASIC verification engineer specializing in UVM, constrained-random, coverage-driven closure, and high-speed protocol validation.

Experience

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Hire the best remote Xilinx Vivado employees

Finding relevant remote workers

28 remote workers

Finding relevant remote workers

vahram sim@vahramsim

Rubeena Tarannum@rubeenatarannum

Noor E Saniya@nooresaniya

Prateeksha Hiremath@prateekshahiremath

dasari lakshmiprasanna@dasarilakshmiprasann

Saad Qureshi@saadqureshi1

Korrapolu Eswar Adithya@korrapolueswaradithy

Keerthi Sree@keerthisree

praveen kumar bolla@praveenkumarbolla

Bhanu Naga Sarika Neelam@bhanunagasarikaneela

Keshava jaya ram Chitturi@keshavajayaramchittu

Aavash Basnet@aavashbasnet

Ahmad Abdullah@ahmadabdullah2

Mahendar Mahi@mahendarmahi

Omkar Gaonkar@omkargaonkar

ANISH MONDAL@anishmondal

SANDHYA CHILUKURI@sandhyachilukuri

Ali Sajjad@alisajjad-dev

Prajyot Patil@prajyotpatil

Andrew Chen@andrewchen4

Find top remote talent

Find top remote talent

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Find your dream job

Find your dream job

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Find your dream job

28 remote workers

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vahram sim@vahramsim

Rubeena Tarannum@rubeenatarannum

Noor E Saniya@nooresaniya

Prateeksha Hiremath@prateekshahiremath

dasari lakshmiprasanna@dasarilakshmiprasann

Saad Qureshi@saadqureshi1

Korrapolu Eswar Adithya@korrapolueswaradithy

Keerthi Sree@keerthisree

praveen kumar bolla@praveenkumarbolla

Bhanu Naga Sarika Neelam@bhanunagasarikaneela

Keshava jaya ram Chitturi@keshavajayaramchittu

Aavash Basnet@aavashbasnet

Ahmad Abdullah@ahmadabdullah2

Mahendar Mahi@mahendarmahi

Omkar Gaonkar@omkargaonkar

ANISH MONDAL@anishmondal

SANDHYA CHILUKURI@sandhyachilukuri

Ali Sajjad@alisajjad-dev

Prajyot Patil@prajyotpatil

Andrew Chen@andrewchen4