Looking for a job

HARI MADDUKURI

@harimaddukuri

Message

I build RTL and FPGA solutions for radar, timing, and hardware validation.

India

Message

What I'm looking for

I'm looking to contribute to RTL, FPGA, ASIC, and verification work involving design, simulation, timing analysis, CDC, hardware bring-up, and debugging.

At Astra Microwave Products, I develop synthesizable RTL for radar control and signal-processing applications, including Timing Control Unit modules and timing-pulse generation logic. I execute FPGA design flows in Xilinx Vivado through simulation, synthesis, implementation, timing analysis, bitstream generation, bring-up, and hardware validation.

Previously at Axiado India, I performed RTL quality checks, CDC and lint analysis, gate-level simulation debugging, and regression testing. I work with SystemVerilog, Verilog, SVA, Synopsys VCS, SpyGlass, QuestaSim, and FPGA debug tools to resolve RTL, timing, and hardware integration issues.

Experience

Work history, roles, and key accomplishments

Current

Senior Engineer

Current

Astra Microwave Products Limited

Nov 2025 - Present (9 months)

Developed synthesizable RTL for radar control and signal processing, executed complete FPGA design flow using Xilinx Vivado, and performed hardware validation and debugging.

RTL Design FPGA UART RS 232 Debugging

Design and Verification Trainee

VLSIGuru

Jan 2023 - Dec 2024 (1 year 11 months)

Completed intensive training in RTL Design, SystemVerilog, SVA, and ASIC verification methodologies, and developed verification projects.

RTL Design SVA ASIC Verification Synopsys VCS

Engineer I

Axiado India Pvt. Ltd.

Nov 2021 - Nov 2022 (1 year)

Performed RTL quality checks using SpyGlass Lint and CDC, debugged Gate-Level Simulations, and executed regression suites using Synopsys VCS and QuestaSim.

Spyglass CDC Linting Synopsys VCS QuestaSim SVA Regression Testing