Prateeksha Hiremath

I am an M.Tech candidate in VLSI & Nanotechnology with hands-on experience in FPGA design, embedded systems, and hardware–software co-design. I combine academic rigor with practical project work to deliver tape-out ready RTL and validated hardware implementations.

During internships at DRDO and CSIR-NAL, I worked with STM32 microcontrollers and implemented a MicroBlaze soft-core with AXI UART Lite, gaining experience in peripheral interfacing, Embedded C, Vivado flows, and Vitis application development. I validated UART loops on an Artix-7 board and participated in system-level testing in a defense R&D environment.

My major projects include taking a UART design from Verilog RTL through Cadence Genus synthesis to Innovus physical layout targeting 90nm, clearing DRC/LVS, and producing a GDSII file. I also designed a 4-bit bit-serial adder optimized for 45nm and proposed a 5G mmWave digital baseband processor architecture emphasizing pipelining and parallelism.

I am eager to join a collaborative, innovation-driven team where I can apply FPGA, VLSI, and embedded expertise to solve real-world problems and continue learning through hands-on development and cross-functional teamwork.