Looking for a job

SiouHua Tsai

@siouhuatsai

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I build and verify FPGA RTL modules for digital systems.

Taiwan

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What I'm looking for

I'm looking to move upstream into FPGA digital design, contributing from architecture and timing design while applying my RTL, protocol validation, and cross-layer debugging experience to improve verification efficiency and system stability.

I've built and verified FPGA RTL for DDR5 IC projects at Powerchip Semiconductor, including SPDHUB, PMIC, and CKD validation.

I developed NVM, MTP, and OTP controllers and behavior models from scratch in Verilog, integrated them on Xilinx 7-series platforms, and used I2C controllers to define packet flows and command sequences.

Previously, at Chao Xuan Technology, I designed panel-control and GOA timing modules on Xilinx FPGA, developed a Verilog SPI write controller, and implemented DAC control logic for PAM pixel driving and 10-bit grayscale modulation.

My work spans RTL, waveforms, protocols, timing constraints, and system-level debugging. I want to contribute earlier in the design process, using my verification perspective to build FPGA architectures with stronger timing quality, validation efficiency, and system stability.

Experience

Work history, roles, and key accomplishments

Current

Engineer

Current

Powerchip Micro Element

Sep 2023 - Present (3 years)

Developed Verilog modules for NVM, MTP, and OTP controllers and integrated them into Xilinx 7-series FPGA platforms for DDR5 IC validation. Performed I3C protocol verification and automated testing with Python SCPI scripts.

Verilog Xilinx 7 Series FPGA I2C I3C SPI Python SCPI (IEEE 488.2)Vivado FPGA NVM MTP OTP DDR5

Engineer

Super Display Technology

Dec 2022 - Aug 2023 (8 months)

Designed FPGA RTL for panel control signals and GOA timing control modules, and developed a Verilog SPI Write Controller for DAC voltage regulation. Assisted in pixel driving circuit design and grayscale modulation.

Verilog FPGA Xilinx SPI DAC Goa PAM APWM Vivado

Education

Degrees, certifications, and relevant coursework

National Sun Yat-sen University

Master's (incomplete), Information Engineering

2016 - 2022

Activities and societies: Embedded Systems Laboratory; RISC-V Soft Core design; AXI bus integration using Vivado IP Integrator.

Graduate studies in Information Engineering with a focus on hardware security, including embedding a Hardware Trojan in a RISC-V Soft Core to bypass detection mechanisms.

Tunghai University

Bachelor of Engineering, Electrical Engineering

2012 - 2016

Activities and societies: Graduation project on power-saving algorithms for wireless sensor network security.

Bachelor's degree in Electrical Engineering, with a graduation project on power-saving algorithms for malicious attack defense in wireless sensor networks.