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vahram sim

@vahramsim

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Junior FPGA design engineer specializing in RTL, verification, and board bring-up.

Armenia

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What I'm looking for

I seek hands-on FPGA design or verification roles where I can work cross-functionally, tackle timing challenges, and drive efficient prototype-to-production delivery.

I am a detail-oriented Junior FPGA Design Engineer with over two years of hands-on experience in RTL design, simulation, and board bring-up, focused on delivering reliable designs for telecom and industrial applications. I have implemented VHDL/Verilog modules, developed UVM-based testbenches, and collaborated closely with firmware and hardware teams to resolve timing issues and streamline production.

I have driven measurable improvements—reducing regression cycles, improving deterministic latency, and automating verification workflows with Python—while contributing to prototype bring-up and synthesis optimization. I bring a practical, results-oriented approach to FPGA architecture, verification, and system integration.

Experience

Work history, roles, and key accomplishments

Junior FPGA Design Engineer

Siemens AG

Aug 2022 - Aug 2024 (2 years)

Implemented and verified VHDL RTL for motor-control and industrial-communication IP, improving deterministic latency by 25% and enabling board bring-up for three prototype revisions while resolving critical timing issues.

RTL Xilinx Vivado Board Bring Up Python

FPGA Design Intern

Infineon Technologies

May 2021 - Aug 2022 (1 year 3 months)

Developed Verilog high-speed serial interface modules and validated them with ModelSim/QuestaSim, automated nightly regressions with Python to cut manual test time by 70% and improved logic utilization by 15%.

Verilog ModelSim QuestaSim Python Synthesis Area Power Reporting Regression Testing

Student Research Assistant

AMD (Xilinx)

Sep 2020 - May 2021 (8 months)

Prototyped accelerator kernels on Zynq UltraScale+ devices achieving a 3x speedup over CPU baseline and documented HLS-to-FPGA flows and user guides for lab toolchains.

HLS Performance Optimization Toolflow Documentation Vivado HLS

Education

Degrees, certifications, and relevant coursework

Technical University of Munich

Master of Science, Electrical Engineering and Information Technology

2018 - 2020

M.Sc. in Electrical Engineering and Information Technology with specialization in digital systems and embedded hardware; thesis on low-latency FPGA architectures for real-time signal processing.

RWTH Aachen University

Bachelor of Science, Electrical Engineering

2015 - 2018

B.Sc. in Electrical Engineering focused on digital logic design, microelectronics, and embedded systems; completed multiple team projects involving FPGA-based system prototypes.