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attar shameerAS
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attar shameer

@attarshameer

I build and improve Vivado FPGA design tools, workflows, and customer-facing documentation at AMD.

India
Message

What I'm looking for

I'm looking to continue building FPGA design tools and workflows, partnering across engineering teams to solve customer-impacting problems and improve developer experience.

At AMD, I architect and drive end-to-end Vivado IDE features including Pblock Planner, DFX Summary Report, and Dark Theme, from specifications and mockups through release.

I re-architected the DFX Wizard for Partial Reconfiguration projects and created Modular NoC-based flow documentation and Quick Take tutorial videos to speed customer onboarding.

I own triage and lifecycle management for Vivado IDE and XSIM issues, translate complex tool behavior into actionable change requests, and bridge GUI and engine teams to improve tooling workflows.

Previously at Xilinx, I provided worldwide front-line support across Vivado, ISE, and HLS Design Suite, partnered with R&D on features and bugs, and authored debugging guides for Vivado HLS and XSIM.

Experience

Work history, roles, and key accomplishments

AMD logoAM
Current

Member of Technical Staff Engineer

Dec 2021 - Present (4 years 9 months)

Architect and drive end-to-end feature development for the Vivado IDE, including Pblock Planner, DFX Summary Report, and Dark Theme support. Own triage, prioritization, and lifecycle management of Vivado IDE and Simulator issues, and maintain documentation across multiple user guides.

Xilinx Inc. logoXI

Product Application Engineer II

Xilinx Inc.

Apr 2017 - Feb 2020 (2 years 10 months)

Provided worldwide front-line technical support for Xilinx Design Tools, resolving issues across Synthesis, RTL Design & Debug, Simulation, Timing & Constraints, IP Flows, TCL scripting, and Implementation. Collaborated with R&D teams on implementing new features and resolving bugs, and authored internal debug guides.

Education

Degrees, certifications, and relevant coursework

C-DAC ACTS, Pune logoCP

C-DAC ACTS, Pune

Post Graduate Diploma, VLSI Design

2016 - 2017

Post Graduate Diploma in VLSI Design from C-DAC ACTS, Pune, from 2016 to 2017.

ST

Srinivasa Ramanujan Institute of Technology

B.Tech, Electronics & Communication Engineering

2012 - 2016

Grade: 79.65%

B.Tech in Electronics & Communication Engineering from Srinivasa Ramanujan Institute of Technology, Anantapur, with 79.65%.

Tech stack

Software and tools used professionally

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