At JSA LAABS, I integrated a custom Spiking Neural Network IP onto a Xilinx Zynq-7000 SoC and developed cycle-accurate SystemVerilog traces that achieved 100% logic parity with PyTorch reference models.
I also wrote bare-metal C drivers in Xilinx Vitis to stream Fashion-MNIST images to the SNN IP, accelerating hardware-software validation cycles by 80%. In my projects, I’ve designed FPGA-based systems for federated learning and video encryption, including a live video encryption project accepted at ACODS ’26.
