Jorge Garza

Architected FPGA requirements for a Torque Measurement System integrated into a mission-critical aerospace propulsion engine controller and developed VHDL on Xilinx UltraScale+ MPSoC using Vitis. Built Python-based XSCT automation and Jenkins/Git/BitBucket CI/CD pipelines for SystemVerilog simulations in QuestaSim, implementing AMBA AXI4 (Full/Lite) for SoC interconnects.

Delivered a PolarFire FPGA design for a 3U VPX IPMI chassis controller through requirements, trade studies, reviews, coding, and verification. Worked in Linux using GitLab, Jenkins, Verilator, and Renode, and documented design status in Confluence.

Redesigned a custom RTL VHDL serial protocol and created a self-checking SystemVerilog testbench. Supported Polarion requirements documentation and implemented AXI4 Full/Lite/Stream integration, building Python-based FPGA lab debug tools using Xilinx ILA and VIO cores.

Migrated legacy RTL from Altera devices to Xilinx Spartan-6, including schematic conversion, megafunction translation, and primitive replacement. Created Python scripts for FPGA smoke testing, updated system-level testbenches, and implemented a 10G Ethernet subsystem tester module on a Virtex UltraScale+ device.

Supported multiple FPGA projects as an RTL design engineer, including legacy requirements capture and source-code migration into configuration management. Developed self-checking UVM testbenches and automated weekly Jenkins build/test cycles, and used MATLAB scripts and lab debug with ILA, JTAG-to-AXI, JTAG-to-AVMM, and Signal Tap.

Implemented an MMCM into a CompactRIO FPGA design to dynamically change LVDS clock rates using Dynamic Reconfiguration Port over AXI4-Lite. Supported a Kintex-7 Xilinx FPGA running on the LabVIEW FPGA platform and contributed to system integration testing support.

Programmed a Xilinx KC705 Kintex-7 development board to gather telemetry over 1Gb Ethernet UDP packets, developing primary RTL in VHDL (with some Verilog). Implemented a DDR3 memory module for data storage and created technical FPGA design and user documentation.

Performed system architecture analysis of vehicle avionics systems and designed hardware-in-the-loop testing apparatus for avionics flight hardware. Programmed a Spartan-7 FPGA solenoid drive board using 1Gb Ethernet UDP packets and installed an RTOS Linux OS onto a Zynq processor FPGA system.

Supported power-systems engineering including sourcing 18650 lithium-ion cells and coordinating mechanical design for an 8-pack battery with NASA Johnson Space Center. Designed active balancing circuitry and a battery management system in Altium, created Simulink test benches for battery characterization, and authored requirements documents.

Designed and implemented FPGA functionality across multiple programs using Altera CPLD and Xilinx Virtex families, developing VHDL interfaces and verification workflows. Built testbenches in QuestaSim, created subsystem test procedures using Simulink, implemented MicroBlaze for debugging, and performed partial reconfiguration tests on a Xilinx Virtex-7 690T.

Set up a test bed to evaluate denial-of-service techniques for IEEE 802.11 networks, including researching compatible hardware/software and implementing a MATLAB GUI for test automation. Conducted testing and documented final results for comparison to previous testing, including familiarity with an azimuth channel emulator.

Built and tested a simulator chassis to exercise MIL-STD-1553 and SpaceWire interfaces for early vehicle integration. Produced assembly/test documentation, executed chassis testing using written procedures, troubleshot issues with engineers, and authored user guides for customer delivery.

Wrote VHDL for a Xilinx Virtex-5 DSP design to output LVDS signals, including implementing an 18-bit LVDS output and creating a memory core for data reads. Verified waveforms in ModelSim, tested outputs on a logic analyzer, and gained experience with VxWorks, Tcl, and VHDL toolchains like ModelSim and Xilinx ISE.

Troubleshot preprocessor boards, debugging C++ software errors in Visual Studio and Workbench and debugging JTAG chains using standard techniques. Assisted in boundary-scan test development for easier troubleshooting and gained experience with Altera toolchains such as Quartus II and Max Plus II.

Pursuing a Master of Space Systems Engineering with an anticipated graduation date of 08/2029.

Earned a Bachelor of Science in Electrical Engineering, graduating in December 2011.