Looking for a job

Puneeth C

@puneethc

Message

R&D intern at Nokia who automated Vivado FPGA design flows for 5G PHY layer RU processing.

India

Message

At Nokia, I automated FPGA design flows for 5G PHY layer RU processing on Xilinx Zynq SoC, using TCL and Vivado to automate RTL synthesis, implementation, and bitstream generation. I also performed IP verification and regression analysis for PHY layer IP blocks.

On my Wireless NOC congestion prediction project, I implemented a Spiking Neural Network and trained a classifier that achieved over 90% congestion prediction accuracy. I’ve also worked on I2C protocol implementation and ANN deployment on FPGA.

Experience

Work history, roles, and key accomplishments

Research and Development Intern

Nokia

Aug 2025 - Jun 2026 (10 months)

Automated FPGA design flows using TCL scripting on Xilinx Zynq SoC for 5G PHY layer RU processing. Performed RTL verification, IP verification, and regression analysis for PHY layer IP blocks.

Tcl Xilinx Vivado Intel Quartus Synopsys Verdi Genus Linux FPGA RTL Verification SystemVerilog UVM Methodology

Education

Degrees, certifications, and relevant coursework

The National Institute of Engineering

Bachelor of Engineering, Electronics and Communication

Grade: 8.3/10

Activities and societies: Related Coursework: Analog Electronics, Digital Electronics, Signals and Systems, Control Systems, Communication Systems, DSP, Wireless Communication, VLSI, Computer Networks, C++ OOP, Data Structures

Pursuing a Bachelor of Engineering in Electronics and Communication with an expected graduation in July 2026. Achieved a GPA of 8.3/10.