Mahendra Naidu Cheekati

At Indian Space Research Organisation (ISRO) – SDSC SHAR, I worked on FPGA-based multi-shaker synchronization using a ZedBoard (Zynq-7000). I developed MATLAB models for signal synchronization and phase correction, validated DSP algorithms, and contributed to FPGA implementation using Xilinx Vivado and Vivado HLS.

At Abhyasa Semicon Technologies, I developed and verified a Verilog memory model using SystemVerilog testbench techniques. I also completed the Foundation Level in Programming and Data Science at IIT Madras.

My ongoing B.Tech major project is a low-power FPGA architecture for real-time ECG arrhythmia detection using DWT, adaptive thresholding, and Binary Neural Networks. Other projects include an ECG signal processing and machine learning pipeline, a 256-bit RTL-to-GDSII implementation, and an IoT-based soil testing kit.