Hire the best remote Synopsys DC employees

Discover remote Synopsys DC workers who are looking for their next full-time, part-time or freelance opportunity on Himalayas.

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20 remote workers

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Keerthi Sree@keerthisree

India

Physical Design Engineer VLSI Design Intern Synopsys ICC2 Dc_shell

VLSI Physical Design Engineer skilled in 28nm PNR flows.

Experience

Mohammed Muneeb@mohammedmuneeb

India

ASIC Design Engineer SOC Engineer Floor Plan Design Placements

VLSI Physical Design engineer focused on timing closure, congestion mitigation, and ASIC/SoC implementation.

Experience

Sneha Garag@snehagarag

India

Physical Design Engineer Layout Specialist RTL To GDSII Flow Clock Tree Synthesis (CTS)

Entry-level VLSI Physical Design Engineer skilled in RTL-to-GDSII flow.

Experience

Pradeep Chowdary Adusumalli@pradeepchowdaryadusu

India

Asic Verification Engineer Timing Analysis Engineer APR Placement Strategy

Physical Design Engineer skilled in low-power, multi-voltage ASIC implementation.

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Himalayas

Ali Sajjad@alisajjad-dev

Pakistan

RTL Design Engineer Verification Engineer Verilog SystemVerilog Assertions

RTL Design and Formal Verification engineer specializing in RISC-V and floating-point units.

Experience

Rajesh Valipi@rajeshvalipi

India

Design Verification Engineer Development Engineer Verilog UVM Environments

I’m a Design Verification Engineer specializing in UVM SystemVerilog protocol and VIP development.

Experience

varchasv t26@varchasvt26

India

DFT Engineering DFT Team Lead Scan Insertion ATPG Verification

DFT engineer specializing in scan insertion, ATPG, and memory test optimization.

Experience

Saravana Rajagobal@saravanarajagobal

Malaysia

VLSI Design Intern FPGA Design Engineer Verilog C

Computer & Communication Systems engineer specializing in semiconductor validation and VLSI.

Experience

Saad Qureshi@saadqureshi1

United States

Digital Designer FPGA Design Engineer Digital Engineering Processes Project Management

Dedicated Electrical Engineer with over ten years of experience.

Experience

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Himalayas

Andrew Chen@andrewchen4

United States

Asic Verification Engineer Design Verification Engineer Verilog UVM Environments

Senior FPGA/ASIC verification engineer specializing in UVM, constrained-random, coverage-driven closure, and high-speed protocol validation.

Experience

Nithu User@nithuuser

India

Verification Engineer UVM Engineer Verilog UVM Methodology

Electronics/ECE graduate specializing in SystemVerilog UVM functional verification.

Experience

Vidhi Radhanpura@vidhiradhanpura

India

Fpga Engineer Verification Engineer UVM Methodology Verilog

Verification engineer specializing in VLSI design and UVM-based functional verification with RTL expertise.

Experience

Battinapati Durga Manohar@battinapatidurgamano

India

Fpga Engineer Senior Verification Engineer Data Structures Verilog

VLSI verification engineer skilled in SystemVerilog/UVM, delivering robust RTL and coverage-driven verification.

Shagufta Mujeeb@shaguftamujeeb

India

Physical Design Engineer Cad Engineer IR Drop Analysis VLSI

VLSI Physical Design Engineer specializing in advanced-node timing closure and PnR automation.

Experience

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Himalayas

Aman K@amank1

India

Verification Engineer Asic Verification Engineer Verilog C++

SoC/IP verification engineer specializing in SV/UVM, protocol VIPs, and debug automation.

Experience

shivraj singh@shivrajsingh

India

Power Systems Engineer FPGA Design Engineer C#Python

Experienced Research & Development Engineer specializing in power analysis.

Experience

Rishith Varma@rishithvarma

India

Physical Design Engineer Place And Route Engineer ASIC Physical Design Place And Route

ASIC Physical Design engineer skilled in block-level PnR, timing closure, and congestion resolution.

Mohit Patle@mohitpatle

India

Mechanical Design Engineer Reliability Engineer Bump Planning Top Metal Power Grid Creation

Senior Physical Design Engineer specializing in floorplan integration and reliability verification.

Experience

Devinda Kulatunge@devindakulatunge

Malaysia

VLSI Design Intern Power Systems Engineer VLSI Power Analysis Python

Electronics Engineer specializing in VLSI Power Analysis and SoC Signoff.

Experience

Mahendar Mahi@mahendarmahi

India

Verification Engineer RTL Design Engineer Verilog C++

VLSI verification engineer specializing in UVM and protocol verification.

Experience

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Sign up now and join over 250,000+ remote workers who receive personalized job alerts, curated job matches, and more for free!

Hire the best remote Synopsys DC employees

Finding relevant remote workers

20 remote workers

Finding relevant remote workers

Keerthi Sree@keerthisree

Mohammed Muneeb@mohammedmuneeb

Sneha Garag@snehagarag

Pradeep Chowdary Adusumalli@pradeepchowdaryadusu

Ali Sajjad@alisajjad-dev

Rajesh Valipi@rajeshvalipi

varchasv t26@varchasvt26

Saravana Rajagobal@saravanarajagobal

Saad Qureshi@saadqureshi1

Andrew Chen@andrewchen4

Nithu User@nithuuser

Vidhi Radhanpura@vidhiradhanpura

Battinapati Durga Manohar@battinapatidurgamano

Shagufta Mujeeb@shaguftamujeeb

Aman K@amank1

shivraj singh@shivrajsingh

Rishith Varma@rishithvarma

Mohit Patle@mohitpatle

Devinda Kulatunge@devindakulatunge

Mahendar Mahi@mahendarmahi

Find top remote talent

Find top remote talent

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Find your dream job

Find your dream job

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Find your dream job

20 remote workers

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Keerthi Sree@keerthisree

Mohammed Muneeb@mohammedmuneeb

Sneha Garag@snehagarag

Pradeep Chowdary Adusumalli@pradeepchowdaryadusu

Ali Sajjad@alisajjad-dev

Rajesh Valipi@rajeshvalipi

varchasv t26@varchasvt26

Saravana Rajagobal@saravanarajagobal

Saad Qureshi@saadqureshi1

Andrew Chen@andrewchen4

Nithu User@nithuuser

Vidhi Radhanpura@vidhiradhanpura

Battinapati Durga Manohar@battinapatidurgamano

Shagufta Mujeeb@shaguftamujeeb

Aman K@amank1

shivraj singh@shivrajsingh

Rishith Varma@rishithvarma

Mohit Patle@mohitpatle

Devinda Kulatunge@devindakulatunge

Mahendar Mahi@mahendarmahi