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Mocharla Mythili

@mocharlamythili

Physical Design Engineer working on Synopsys ICC2 chip design, including floorplanning, CTS, routing, and timing sign-off.

India

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What I'm looking for

I'm eager to contribute to innovative semiconductor projects while continuously learning and growing.

My 14nm Chiptop Physical Design Project gave me hands-on experience executing full-chip physical design with Synopsys ICC2. I worked on chiptop floorplanning, multi-voltage power planning, congestion-aware placement, CTS optimization, routing, and timing sign-off with DRC/LVS.

My physical design work also includes STA, physical verification, and TCL scripting, using ICC2, PrimeTime, and StarRC.

For a separate project, I developed a decision tree-based passive islanding detection system for distributed power systems. I analyzed voltage and current parameters and used MATLAB and Simulink to evaluate the system through data analysis and simulation.

Experience

Work history, roles, and key accomplishments

Physical Design Engineer

APCPDCL

May 2024 - Jun 2024 (1 month)

Completed a 6-week technical training on Power Distribution Systems and Substation Operations. Analyzed real-time operations of 33/11 kV substations, protective relays, and distribution transformer load monitoring practices.

Power Distribution Systems Substation Operations Protective Relaying Load Monitoring Feeder Management Fault Isolation