Harshan K

I’m an Electronics and Communication Engineering graduate focused on ASIC physical design, with a strong RTL foundation across digital design, RTL design, and Verilog HDL. I’m hands-on with the complete RTL-to-GDSII flow and I’m comfortable turning timing/debug insights into actionable implementation changes.

In my current role as a Physical Designer Trainee, I execute the complete RTL-to-GDSII implementation using Synopsys Design Compiler, ICC2, PrimeTime, and StarRC. I work on setup and hold violation analysis and closure, gain exposure to OCV, AOCV, MCMM, and ECO implementation methodologies, and automate implementation tasks with Tcl scripting. I also perform parasitic extraction using StarRC and timing signoff using PrimeTime to support robust timing closure.

My project work reinforces my ability to design, simulate, and validate: I implemented SHA-256 in Verilog HDL with Vivado simulation, using a modular RTL structure and FSM-based control, then verified outputs with waveform-driven debugging. I also completed a SynopNex28 physical design implementation in 28nm for a 61K-cell design with 40 macros and 4 clock domains, covering floorplanning, power planning, placement, CTS, and routing in ICC2, and finishing timing signoff with StarRC and PrimeTime. I optimize for quality and reliability, and I’m eager to contribute—including to Formal Verification—by leveraging my analytical approach, RTL understanding, and passion for dependable hardware.