Sneha Garag

I am an entry-level VLSI Physical Design Engineer with hands-on training in RTL-to-GDSII flow, STA, and physical verification using Synopsys EDA tools.

During a focused six-month traineeship, I completed full-chip physical design tasks for 28nm and 14nm nodes, including import, floorplanning, power planning, placement, CTS, routing, RC extraction and timing closure.

I have executed multiple technology-node projects (14nm and 28nm) using Synopsys ICC2, Design Compiler, PrimeTime and StarRC, resolving DRC/LVS issues and applying ECO fixes for timing, congestion and signal integrity.

I bring strong analytical thinking, clear communication skills, and practical experience with Verilog, TCL and Python, and I am eager to contribute to semiconductor design projects and grow within a chip-design team.