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Sneha Garag

@snehagarag

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Entry-level VLSI Physical Design Engineer skilled in RTL-to-GDSII flow.

India

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What I'm looking for

I am seeking an entry-level VLSI physical design role where I can apply RTL-to-GDSII skills, work on 14/28nm flows, collaborate with a hands-on chip-design team, and grow technical expertise in timing and physical verification.

I am an entry-level VLSI Physical Design Engineer with hands-on training in RTL-to-GDSII flow, STA, and physical verification using Synopsys EDA tools.

During a focused six-month traineeship, I completed full-chip physical design tasks for 28nm and 14nm nodes, including import, floorplanning, power planning, placement, CTS, routing, RC extraction and timing closure.

I have executed multiple technology-node projects (14nm and 28nm) using Synopsys ICC2, Design Compiler, PrimeTime and StarRC, resolving DRC/LVS issues and applying ECO fixes for timing, congestion and signal integrity.

I bring strong analytical thinking, clear communication skills, and practical experience with Verilog, TCL and Python, and I am eager to contribute to semiconductor design projects and grow within a chip-design team.

Experience

Work history, roles, and key accomplishments

Physical Design Project Engineer

N/A

Jan 2025 - Jun 2025 (5 months)

Led multiple 14nm and 28nm node physical-design projects handling import, floorplanning, placement, CTS, routing, RC extraction and timing analysis for multi-macro designs targeting 1GHz operation.

Clock Tree Synthesis Routing RC Extraction

VLSI Physical Design Trainee

Chipedge Technologies Pvt Ltd

Jan 2025 - Jun 2025 (5 months)

Completed hands-on RTL-to-GDSII physical design training for 28nm and 14nm nodes, executing floorplanning, power planning, placement, CTS, routing and achieving timing closure with STA and DRC/LVS verification.

RTL To GDSII Flow Synopsys ICC2 Design Compiler StarRC RC Extraction Tcl Verilog