Pallavi Das

Senior Staff Engineer at Samsung Semiconductor, focusing on physical design and timing closure.

Worked as SOC Design Engineer at Intel Corporation.

Worked as Physical Design Engineer at Synopsys Inc.

*Good understanding of RTL to GDSII flow
*Familiar with different flows and methodologies (MCMM and MV flows)
*Expertise in Synopsys backend tool IC Compiler-II
*Focused mainly on physical implementation & timing closure flow with synthesis, formal equivalence,placement, optimization, low power checks, CTS , routing, crosstalk delay/noise analysis etc using Synopsys tools
* Compared and analysed v

Worked as Research And Teaching Assistant at Indraprastha Institute of Information Technology, Delhi.

-Development of Real Value Modeling (RVM) methodology to incorporate true analog behavior of AMS IPs in Verilog through WREAL modeling technique. The technique has been successfully used in modeling PLL analog loop behavior in Verilog.
- Behavioral model development of PLLs, voltage regulators in Verilog
- Worked on Deployment of equivalence checking methodology for clock generation, Thermal Sens

Pursued a Master of Technology in VLSI and Embedded Systems, focusing on advanced VLSI design and embedded system concepts.

Graduated with Honours in Electronics and Telecommunication

Graduated with Honours in Electronics and Telecommunication, building a strong foundation in electronic systems and communication.