Mohammed Muneeb

I’m a motivated, detail-oriented ECE graduate with a strong interest in VLSI Physical Design, ASIC implementation, and SoC design. I’ve trained in floorplanning, placement, CTS, routing, STA, congestion analysis, IRdrop, and DRC/LVS debugging to support clean, sign-off-ready implementations.

My work is hands-on with Synopsys tools—using Synopsys ICC2 for implementation and Synopsys PrimeTime for timing-focused verification. I aim to deliver timing closure through practical optimization, while maintaining physical integrity via congestion mitigation, local density optimization, and robust physical sign-off checks.

In projects like CHIP_TOP (14nm, ~105MHz), ORCA (32nm, ~125MHz), and ORCA (14nm, ~66.66MHz), I executed end-to-end physical design flows: floorplanning, powerplanning, placement, CTS, routing, and STA. I resolved timing violations, congestion issues, and DRC/LVS violations—strengthening my confidence in macro-aware implementation, routing quality, skew balancing, and missing-via fix flows across multiple clock domains.

I’m also committed to reliability-minded design through my B.Tech major project on a Fault-Tolerant IIR Filter using CRC, which improved error detection and fault tolerance for digital signal processing systems. With training from VLSI FIRST and recognition like “BestProject” for a Fuel Theft Detection System, I bring a learning-driven, high-performance semiconductor mindset to every implementation task.