Rozet Khacheryan

RK

Open to opportunities

Rozet Khacheryan

@rozetkhacheryan

STA/Analog Design Engineer who generated timing libraries for analog blocks and resolved timing-path issues.

What I'm looking for

My primary objective is to support the functioning of business operations and create a positive, productive work environment by communicating with team members.

At Synopsys Educational Department, I completed standard-cell layout work as an intern. I later worked on USB host controller design, fixing lint violations, debugging signals, and running regressions with SpyGlass.

As an Engineer in STA/Analog design, I performed static timing analysis for analog blocks. I generated timing corners and libraries, checked back-annotation issues, and addressed timing issues such as false paths.

Experience

Work history, roles, and key accomplishments

SD

STA/Analog Design Engineer

Synopsys Educational Department

Sep 2024 - Nov 2025 (1 year 2 months)

Performed static timing analysis for analog blocks, generating corners, running pre and post LPE analyses, and fixing missing or extra arcs. Generated libraries and checked back annotation issues.

STA Analog Design Custom Compiler Nanotime LPE Liberty Static Timing Analysis

SD

ASIC Digital Design Intern

Synopsys Educational Department

Oct 2022 - Oct 2023 (1 year)

Worked on USB host controller design, fixing lint violations and debugging signals. Ran regressions and generated clean Verilog code.

ASIC Digital Design Verilog Linting Debugging Spyglass regression

SD

Intern

Synopsys Educational Department

Jun 2022 - Oct 2022 (4 months)

Performed layout design for standard cells as part of an internship at Synopsys Educational Department.

Layout Standard Cells Custom Design

Education

Degrees, certifications, and relevant coursework

YU

Yerevan State University

Bachelor's and Master's, Physics

Pursued a Bachelor's and Master's degree at the YSU Physics Department.

SD

Synopsys Educational Department

Graduate, Engineering

Completed education at the Synopsys Educational Department, focusing on engineering skills.

Tech stack

Software and tools used professionally

Linux

Verilog

Availability

Open to opportunities

Location

Armenia

Authorized to work in

Salary expectations

60k+ USD

Job categories

ASIC Design Engineer

Skills

Static Timing Analysis Analog Design Digital Design ASIC Design Custom Design Flow Digital Design Flow Digital Logic Verification Standard Cell Layout Timing Libraries Multi Mode Files Back Annotation False Path Analysis Linting Regression Testing

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