I've delivered analog and mixed-signal layouts across Samsung 2nm and TSMC 3nm, 7nm, 16nm, 40nm, and 90nm technologies, taking PLL, IO, memory, and high-voltage components from schematic through clean physical verification.
At Digicomm Semiconductor, I owned high-speed PLL macro delivery, IO top-level integration for 46 complex cells, and mixed-signal IP layouts. I resolved EM/IR issues, applied matching and shielding methodologies, and built ESD structures, level shifters, drivers, buffers, and other high-voltage components.
At Nvidia Graphics, I built custom memory layouts including Row Decoder and Local I/O blocks at TSMC 3nm. I use Cadence Virtuoso, Calibre, Synopsys ICV, and layout automation practices to deliver robust DRC, LVS, ERC, density, and reliability closure.
