Nishchay kumar M

NM

Looking for a job

Nishchay kumar M

@nishchaykumarm

VLSI Physical Design fresher trained at VLSI First Training Institute who achieved timing closure on ORCA and ChipTop Processor.

What I'm looking for

I'm seeking a fresher role in VLSI Physical Design. I'm an immediate joiner, open to relocating, and eager to learn from experienced engineers while contributing to the team.

At VLSI First Training Institute, I completed two block-level RTL-to-GDSII projects: ORCA and ChipTop Processor.

Using Synopsys ICC2, I achieved timing closure on both projects by fixing setup and hold violations through cell sizing and buffer insertion. I also reduced routing congestion and cleared max transition, max capacitance, and DRC violations.

I use TCL to automate flows and extract reports, and I also work with Python and Verilog. As a 2025 Electronics and Communication Engineering graduate, I'm seeking a fresher role in VLSI Physical Design.

Experience

Work history, roles, and key accomplishments

VI

VLSI Physical Design Trainee

VLSI First Training Institute

Completed two block-level RTL-to-GDSII projects using Synopsys ICC2, achieving timing closure and reducing routing congestion.

Physical Design Synopsys ICC2 Tcl Python Verilog Timing Closure DRC

Education

Degrees, certifications, and relevant coursework

VI

VLSI First Training Institute

Training, VLSI Physical Design

Completed two block-level RTL-to-GDSII projects using Synopsys ICC2, achieving timing closure and clearing DRC violations.

Tech stack

Software and tools used professionally

Python

Verilog

Availability

Looking for a job

Location

India

Authorized to work in

Salary expectations

70k+ INR

Job categories

ASIC Physical Design Engineer

Skills

Physical Design RTL To GDSII Timing Closure Setup Hold Analysis Cell Sizing Buffer Insertion Routing Congestion Reduction DRC Max Transition Analysis Max Capacitance Analysis Tcl Synopsys ICC2 Python Verilog

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