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Pradeep Chowdary Adusumalli

@pradeepchowdaryadusu

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Physical Design Engineer skilled in low-power, multi-voltage ASIC implementation.

India

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What I'm looking for

I seek a role in ASIC physical design where I can work on low-power, multi-voltage blocks, contribute to timing and power closure, and build automated, reliable flows within a collaborative engineering team.

I am a Physical Design Engineer with hands-on experience implementing low-power, multi-voltage ASIC flows on 40nm technology using Synopsys ICC2, Innovus and PrimeTime. I have executed floorplanning, power planning, CTS, routing, signoff checks and timing closure across multi-domain designs while automating flows with TCL/Perl.

I delivered a 0.4M-gate, dual-supply block operating at 1 GHz, maintained power and IR-drop budgets, resolved DRC/LVS/antenna issues and debugged complex MCMM timing corners. I emphasize reliable, automated physical flows and practical problem-solving to meet performance, power and manufacturability goals.

Experience

Work history, roles, and key accomplishments

ASIC Physical Design Intern

RV-Skills Center for Emerging Technologies

Mar 2025 - Sep 2025 (6 months)

Implemented a 40nm low-power ASIC physical design flow across 9 power domains using Synopsys ICC2, achieving timing closure and signoff-quality DRC/LVS fixes while meeting a 450 mW power budget for a 0.4M-gate block.

ASIC Physical Design Synopsys ICC2

Physical Design Project Lead

Chalapathi Institute of Technology

Designed and implemented a high-speed, low-power 13T hybrid full adder in 180nm using Tanner EDA, achieving reduced power-delay product and smaller area versus conventional designs.

Tanner EDA CMOS Full Adder RTL To GDS Layout

Education

Degrees, certifications, and relevant coursework

RVSkills Design Centre, Bengaluru

Advanced Diploma in ASIC Design, ASIC/Physical Design

2025 - 2025

Advanced Diploma in ASIC Design with specialization in Physical Design completed between March 2025 and September 2025 focusing on APR, floorplanning, CTS, routing, and signoff flows.

Chalapathi Institute of Technology

Bachelor of Engineering, Electronics and Communication

2022 - 2025

Grade: 7.79 CGPA

Bachelor of Engineering in Electronics and Communication completed with a 7.79 CGPA, involving projects on high-speed hybrid full adder and IoT-based rescue systems.